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    MEMORY SYSTEM
    1.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240274185A1

    公开(公告)日：2024-08-15

    申请号：US18438635

    申请日：2024-02-12

    申请人： Kioxia Corporation

    发明人： Naomi TAKEDA ,  Masanobu SHIRAKAWA

    IPC分类号： G11C11/4096 ,  G11C11/4076 ,  G11C29/52

    CPC分类号： G11C11/4096 ,  G11C11/4076 ,  G11C29/52

    摘要： According to one embodiment, a memory system includes: a non-volatile memory including blocks each including memory cells; and a memory controller configured to execute a first read process of reading data from a first memory cell in a first block by using a first voltage and a second read process of reading data from a second memory cell in the first block by using a second voltage. The memory controller is configured to: maintain, when a first condition is satisfied, a difference between the first and second voltages at a first value, and change both the first and second voltages; and change, when a second condition is satisfied after the first condition has been satisfied, a difference between the first and second voltages from the first value to a second value, and change at least one of the first and second voltages.

    MEMORY SYSTEM AND METHOD
    4.
    发明公开
    MEMORY SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20240055065A1

    公开(公告)日：2024-02-15

    申请号：US18230151

    申请日：2023-08-03

    申请人： Kioxia Corporation

    发明人： Ryo YAMAKI ,  Masanobu SHIRAKAWA ,  Naomi TAKEDA ,  Takashi NAKAGAWA ,  Shingo YANAGAWA

    IPC分类号： G11C29/12

    CPC分类号： G11C29/12005 ,  G11C2029/1202

    摘要： According to one embodiment, a memory system includes a non-volatile first memory with first storage areas. A controller executes a first read operation on a second storage area of the first storage areas. When an error correction in the first read operation fails, the controller acquires a first measured value being a value of a read voltage for suppressing the number of occurrences of error bits in the second storage area. The controller updates, on the basis of the first measured value, one of first candidate values of the read voltage with a second candidate value. When the error correction in a second read operation for a third storage area of the first storage areas fails, the controller executes the read operation once or more on the third storage area by using, as the read voltages, different first candidate values of the first candidate values.

    MEMORY SYSTEM
    5.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230187008A1

    公开(公告)日：2023-06-15

    申请号：US18163906

    申请日：2023-02-03

    申请人： Kioxia Corporation

    发明人： Naomi TAKEDA ,  Masanobu SHIRAKAWA

    IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/18

    CPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C2029/1204

    摘要： According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.

    MEMORY SYSTEM AND MEMORY DEVICE
    6.
    发明申请
    MEMORY SYSTEM AND MEMORY DEVICE 有权

    公开(公告)号：US20220130458A1

    公开(公告)日：2022-04-28

    申请号：US17647229

    申请日：2022-01-06

    申请人： Kioxia Corporation

    发明人： Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Akio SUGAHARA

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

    摘要： According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

    STORAGE DEVICE AND MEMORY CONTROLLER
    7.
    发明申请
    STORAGE DEVICE AND MEMORY CONTROLLER 有权

    公开(公告)号：US20210089233A1

    公开(公告)日：2021-03-25

    申请号：US16816439

    申请日：2020-03-12

    申请人： Kioxia Corporation

    发明人： Yoshihiro UEDA ,  Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Marie TAKADA

    IPC分类号： G06F3/06 ,  G06F11/10 ,  G06F12/10

    摘要： According to one embodiment, a storage device includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of storage blocks, each including a shift register. The control circuit controls writing and reading of data to and from the nonvolatile memory. The control circuit is configured to: read target data from a first storage block of the plurality of storage blocks; and write the target data read from the first storage block to a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block.

    MEMORY SYSTEM
    8.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220101901A1

    公开(公告)日：2022-03-31

    申请号：US17550338

    申请日：2021-12-14

    申请人： Kioxia Corporation

    发明人： Naomi TAKEDA ,  Masanobu SHIRAKAWA

    IPC分类号： G11C11/16 ,  G06F9/30

    摘要： According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter.

    MEMORY SYSTEM
    9.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220093198A1

    公开(公告)日：2022-03-24

    申请号：US17158161

    申请日：2021-01-26

    申请人： Kioxia Corporation

    发明人： Naomi TAKEDA ,  Ryo YAMAKI ,  Masanobu SHIRAKAWA

    IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/40 ,  G11C29/18 ,  G11C29/12

    摘要： According to one embodiment, a memory system includes a nonvolatile memory including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells, and a memory controller. The memory controller is configured to: read first data from a first cell unit, using a first correction amount of a read voltage; identify an address of an error bit in the first data; update the first correction amount to a second correction amount, based on the first data and the address of the error bit of the first data; and read second data from a second cell unit different from the first cell unit, using a third correction amount based on the second correction amount.