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公开(公告)号：US20230170027A1
公开(公告)日：2023-06-01
申请号：US18104349
申请日：2023-02-01
Applicant: Kioxia Corporation
Inventor： Takashi MAEDA
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/08 , H10B43/27 , H10B43/35 , G11C16/14 , G11C16/26 , G11C16/10 , G11C5/145
Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
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公开(公告)号：US20220011963A1
公开(公告)日：2022-01-13
申请号：US17197667
申请日：2021-03-10
Applicant: Kioxia Corporation
Inventor： Tomoya SANUKI , Yuta AIBA , Hitomi TANAKA , Masayuki MIURA , Mie MATSUO , Toshio FUJISAWA , Takashi MAEDA
IPC: G06F3/06
Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of −40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of −40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.
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公开(公告)号：US20250095743A1
公开(公告)日：2025-03-20
申请号：US18829434
申请日：2024-09-10
Applicant: Kioxia Corporation
Inventor： Tatsuo OGURA , Masaki KONDO , Takashi MAEDA
Abstract: A semiconductor memory device includes: a first conductive layer; and a second conductive layer adjacent to the first conductive layer. Write loops each include: a first program operation that applies the first conductive layer with a program voltage and applies a bit line with a first bit line voltage; and a second program operation that applies the first conductive layer with the program voltage and applies the bit line with a second bit line voltage larger than the first bit line voltage. The write operation includes a state judging operation that judges whether a memory cell corresponding to the semiconductor layer and the second conductive layer has been controlled to a Low-state, or not. When the memory cell has been controlled to the Low-state, the first program operation is executed, and when the memory cell has not been controlled to the Low-state, the second program operation is executed.
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Patent Agency Ranking
公开(公告)号：US20240062822A1
公开(公告)日：2024-02-22
申请号：US18500520
申请日：2023-11-02
Applicant: Kioxia Corporation
Inventor： Rieko FUNATSUKI , Takashi MAEDA
Abstract: A semiconductor memory device includes a first to eighth memory cell groups arranged along a first direction, a first word line extending in the first direction and a first to an eighth sense amplifier groups configured to be capable of supplying voltages to the first to the eighth memory cell groups, respectively. Each of the first to the eighth memory cell groups includes a plurality of memory cells and a plurality of bit lines each connected to the plurality of memory cells. In a write operation of supplying a program voltage to the first word line, the first sense amplifier group supplies a first voltage to the bit line connected to a write target memory cell of the first memory cell group, and the second sense amplifier group supplies a second voltage to the bit line connected to a write target memory cell of the second memory cell group.
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公开(公告)号：US20230197148A1
公开(公告)日：2023-06-22
申请号：US17806346
申请日：2022-06-10
Applicant: Kioxia Corporation
Inventor： Rieko FUNATSUKI , Takashi MAEDA , Hidehiro SHIGA
CPC classification number: G11C11/5642 , G11C11/5628 , G11C11/5671 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/0483 , G11C16/3459
Abstract: A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.
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公开(公告)号：US20220284962A1
公开(公告)日：2022-09-08
申请号：US17445614
申请日：2021-08-23
Applicant: Kioxia Corporation
Inventor： Kazutaka IKEGAMI , Takashi MAEDA
Abstract: A memory system according to an embodiment includes first to sixth word lines, a plurality of memory pillars and a control circuit. The control circuit performs an initial write operation in which a threshold voltage of a subject memory cell is increased from a first level to a second level, a first write operation after the initial write operation and a second write operation after the first write operation. The control circuit is configured to perform the initial write operation on the third memory cell and the fourth memory cells, the first write operation on the third memory cells, the first write operation on the fourth memory cells, the second write operation on the fifth memory cells, the second write operation on the sixth memory cells, and the initial write operation on the first memory cells and the second memory cells.
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公开(公告)号：US20220084608A1
公开(公告)日：2022-03-17
申请号：US17199718
申请日：2021-03-12
Applicant: Kioxia Corporation
Inventor： Shingo NAKAZAWA , Takashi MAEDA
Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.
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公开(公告)号：US20210090665A1
公开(公告)日：2021-03-25
申请号：US16906140
申请日：2020-06-19
Applicant: Kioxia Corporation
Inventor： Rieko FUNATSUKI , Takahiko HARA , Takashi MAEDA
Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.
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