公开(公告)号：US4707720A

公开(公告)日：1987-11-17

申请号：US802372

申请日：1985-11-27

申请人： Koji Shirai ,  Ken Kawamura

发明人： Koji Shirai ,  Ken Kawamura

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/73 ,  H01L29/78 ,  H01L29/04

CPC分类号： H01L29/404 ,  H01L29/405 ,  H01L29/7302 ,  H01L29/7322 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7809

摘要： There is disclosed an NPN transistor comprising collector region of N conductivity type, base region of P conductivity type formed in the collector region, and emitter region of N conductivity type formed in the collector region. The collector and emitter regions define therebetween a planar PN junction. The NPN transistor further comprises a field plate electrode layer, when the transistor is viewed from above, extending from the periphery of the base region to the collector region. The field plate electrode layer comprises P conductivity semiconductor portion and N conductivity semiconductor portion. The P conductivity semiconductor portion is on the side of the base region. The N conductivity semiconductor portion is on the side of the collector region.

摘要翻译： 公开了一种NPN晶体管，其包括N导电类型的集电极区域，在集电极区域形成的P导电类型的基极区域和形成在集电极区域中的N导电类型的发射极区域。 集电极和发射极区域在其间限定平面PN结。 当从上方观察晶体管时，NPN晶体管还包括场板电极层，从基极区域的周边延伸到集电极区域。 场极板电极层包括P导电半导体部分和N导电半导体部分。 P导电性半导体部位于基极侧。 N导电性半导体部位于集电极区域侧。

公开(公告)号：US20090068569A1

公开(公告)日：2009-03-12

申请号：US12230838

申请日：2008-09-05

申请人： Tsutomu Seta ,  Koji Shirai

发明人： Tsutomu Seta ,  Koji Shirai

IPC分类号： G03F7/004

CPC分类号： G03F7/001 ,  G03F7/027

摘要： The sensitivity, diffraction efficiency, etc. of hologram recording materials is improved. Disclosed is a resin composition for a hologram recording material, the resin composition comprising: a photosensitive component comprising (a) a monomer having a vinyloxy group, (b) a compound having a (meth)acryloxy group, and (c) a photopolymerization initiator; and a prepolymer component, wherein the component (a) is designed so as to be relatively higher or lower in refractive index than the prepolymer component.

摘要翻译： 提高了全息记录材料的灵敏度，衍射效率等。 公开了一种用于全息记录材料的树脂组合物，该树脂组合物包括：感光组分，其包含（a）具有乙烯氧基的单体，（b）具有（甲基）丙烯酰氧基的化合物和（c）光聚合引发剂 ; 和预聚物组分，其中组分（a）被设计成折射率比预聚物组分相对更高或更低。

公开(公告)号：US06731958B1

公开(公告)日：2004-05-04

申请号：US09495450

申请日：2000-02-01

申请人： Koji Shirai

发明人： Koji Shirai

IPC分类号： H04B138

CPC分类号： H04W52/027 ,  Y02D70/26

摘要： A portable radio communication apparatus which allows reduction in power consumption is disclosed. An input device has a special key and a plurality of general keys. A microprocessor changes an operation mode from a power-saving mode to a normal operation mode when receiving an interrupt signal. A controller connected to the special key outputs the interrupt signal to the microprocessor when one of the general keys is operated. When the special key is operated, the controller controls a backlit LCD without outputting the interrupt signal such that the LCD is backlighted and predetermined information is displayed on the LCD.

摘要翻译： 公开了一种能够降低功耗的便携式无线通信装置。 输入设备具有特殊键和多个通用键。 当接收到中断信号时，微处理器将操作模式从功率节省模式改变为正常操作模式。 连接到特殊键的控制器在其中一个常规键被操作时将中断信号输出到微处理器。 当特殊键操作时，控制器控制背光LCD而不输出中断信号，使得LCD背光，LCD上显示预定信息。

公开(公告)号：US5306938A

公开(公告)日：1994-04-26

申请号：US777004

申请日：1991-10-16

申请人： Koji Shirai

发明人： Koji Shirai

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/784 ,  H01L29/68

CPC分类号： H01L29/42368 ,  H01L29/0821 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7322 ,  H01L29/7835

摘要： A lateral MOSFET includes a back gate region, a part of its surface being a channel region. The back gate region surrounds the drain region, while being in contact with a part of the periphery of the drain region. With this configuration, when a high voltage electrostatic surge appears at the drain electrode, a surge current will disperse from the drain region toward the surrounding back gate region. As a result, a rise in the electric potential at the drain region is suppressed. Thus, the electric potential will not exceed the dielectric strength of the gate insulating film to suppress a breakdown of the gate insulating film and an electrostatic breakdown of the device.

摘要翻译： 横向MOSFET包括背栅区，其表面的一部分是沟道区。 背栅极区域围绕漏极区域，同时与漏极区域的周边的一部分接触。 利用这种配置，当在漏电极处出现高电压静电浪涌时，浪涌电流将从漏极区域分散到周围的背栅极区域。 结果，抑制了漏极区域的电位的上升。 因此，电位不会超过栅极绝缘膜的介电强度，以抑制栅绝缘膜的击穿和器件的静电击穿。

公开(公告)号：US5202573A

公开(公告)日：1993-04-13

申请号：US689743

申请日：1991-05-21

申请人： Koji Shirai

发明人： Koji Shirai

IPC分类号： H01L29/74 ,  H01L21/822 ,  H01L27/06 ,  H01L29/739 ,  H01L29/747 ,  H01L29/749

CPC分类号： H01L29/7393 ,  H01L29/747 ,  H01L29/749

摘要： A semiconductor layer made of an epitaxial growing layer (16) is formed on the surface of a p.sup.- -type silicon semiconductor substrate (11), first impurity regions are formed by p.sup.+ -type buried regions (171, 172) and a p-type impurity regions (221, 222) throughout the semiconductor layer from its surface to the semiconductor substrate so as to divide said semiconductor layer into side element regions (161, 162) and a central island region (163). An anode layer obtained by alternately arranging n.sup.+ -type impurity regions (251 to 253) and p.sup.+ -type impurity regions (231, 232) is formed in surface regions of the pair of impurity regions, and cathode regions made of p-type impurity regions (231, 232) are formed in the element regions of the semiconductor layer. Gate electrodes are formed to be opposite to each other through a gate insulating film in p-n junction portions constituted by the n.sup.+ -type impurity regions (251, 252) the p-type impurity regions (221, 222), and an n.sup.- -type element region which are exposed on the surface of the substrate, thereby constituting a pair of MOS thyristors made of a p-n-p-n junction arranged in a lateral direction.

摘要翻译： PCT No.PCT / JP90 / 01295 Sec。 371日期1991年5月21日 102（e）日期1991年5月21日PCT提交1990年10月5日PCT公布。 出版物WO91 / 05372 日期：1991年04月18日。在p型硅半导体衬底（11）的表面上形成由外延生长层（16）制成的半导体层，第一杂质区由p +型掩埋区（171 ，172）和从其表面到半导体衬底的整个半导体层的p型杂质区（221,222），以便将所述半导体层分成侧元件区（161,162）和中心岛区（163） 。 在一对杂质区域的表面区域形成由n +型杂质区域（251〜253）和p +型杂质区域（231,232）交替排列而得到的阳极层，由p型杂质区域 （231,232）形成在半导体层的元件区域中。 栅电极通过由n +型杂质区域（251,252），p型杂质区域（221,222）和n型杂质区域构成的pn结部分中的栅极绝缘膜彼此相对地形成， 元件区域，其暴露在基板的表面上，从而构成由横向布置的pnpn结构成的一对MOS可控硅。

公开(公告)号：US5191401A

公开(公告)日：1993-03-02

申请号：US789444

申请日：1991-11-07

申请人： Koji Shirai ,  Ken Kawamura

发明人： Koji Shirai ,  Ken Kawamura

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L27/0922 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/41758

摘要： A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first well of a second conductivity type formed on the semiconductor substrate of the first conductivity type, a first impurity diffusion layer of the first conductivity type formed on the well without contacting the semiconductor substrate, a second impurity diffusion layer of the second conductivity type which surrounds the first impurity diffusion layer and has an impurity concentration which is higher than that of the first impurity diffusion layer, a third impurity diffusion layer of the first conductivity type formed within the second impurity diffusion layer so as to contact neither the semiconductor substrate nor the first impurity diffusion layer, a source electrode connected to both the second impurity diffusion layer and the third impurity diffusion layer, a gate electrode which is formed between the first impurity diffusion layer and the third impurity diffusion layer and formed on the second impurity diffusion layer so as to interpose an insulation film therebetween, a drain electrode connected to the first impurity diffusion layer, and a wiring layer extracted from the drain electrode outside the semiconductor substrate.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在第一导电类型的半导体衬底上的第二导电类型的第一阱，第一导电类型的第一杂质扩散层形成在阱上而不接触半导体 衬底，第二导电类型的第二杂质扩散层围绕第一杂质扩散层并且具有比第一杂质扩散层的杂质浓度高的杂质浓度;第二导电类型的第三杂质扩散层形成在第二杂质扩散层的第二杂质扩散层内 杂质扩散层，既不与半导体衬底也不接触第一杂质扩散层，连接到第二杂质扩散层和第三杂质扩散层两者的源电极，形成在第一杂质扩散层和第二杂质扩散层之间的栅电极 第三杂质扩散层，形成在第三杂质扩散层上 e第二杂质扩散层，以在其间插入绝缘膜，连接到第一杂质扩散层的漏电极和从半导体衬底外部的漏电极提取的布线层。

公开(公告)号：US5108944A

公开(公告)日：1992-04-28

申请号：US413006

申请日：1989-09-26

申请人： Koji Shirai ,  Ken Kawamura

发明人： Koji Shirai ,  Ken Kawamura

IPC分类号： H01L21/336 ,  H01L21/761 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823462 ,  H01L21/761 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/088 ,  Y10S148/031 ,  Y10S148/082

摘要： In a semiconductor device according to the present invention, a pair of element regions of a second conductivity type are formed so as to be electrically isolated from each other on a semiconductor substrate of a first conductivity type, a complementary MOS transistor is formed in one of the element regions of the second conductivity type, and a double-diffused MOS transistor is formed in the other element region of the second conductivity type. The complementary MOS transistor is of a surface channel type in which N- and P-channel MOS transistors are respectively formed in a pair of well diffusion layers of the first and second conductivity types formed in the element region of the second conductivity type, and conductivity types of the respective gate electrodes of the N- and P-channel MOS transistors are different from those of the respective well diffusion layers. The double-diffused MOS transistor is of a surface channel type in which a back gate region is formed so as to be self-aligned with the gate electrode and the conductivity type of the gate electrode is different from that of the well diffusion layer.

公开(公告)号：US5059547A

公开(公告)日：1991-10-22

申请号：US412149

申请日：1989-09-25

申请人： Koji Shirai

发明人： Koji Shirai

IPC分类号： H01L21/322 ,  H01L21/762 ,  H01L27/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7824 ,  H01L21/3226 ,  H01L21/76251 ,  H01L27/0688 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/78654 ,  H01L29/42368 ,  H01L2924/0002 ,  Y10S148/012

摘要： First and second single crystal silicon substrates are integrated, by means of a thermal treatment, with first and second silicon oxide films formed on surfaces of said respective first and second single crystal silicon substrates in contact with each other. More specifically, an insulating region is formed by integrating first and second silicon oxide films formed on the first and second single crystal silicon substrates. First and second semiconductor regions constituted by the first and second single crystal silicon substrates are electrically isolated by the insulating region. As a result, it is possible to reduce the width of the depletion layer generated in the second semiconductor region by the influence of the first semiconductor region in which an element is formed. A back gate region formed in the second semiconductor region and the first semiconductor region, in which an element is not formed, are held substantially at an equal potential. In this way, it is possible to improve the yield voltage characteristics between the first semiconductor region, which does not form any element, and the back gate region. The insulating region which electrically isolates the first and second semiconductor regions from each other, is formed by bonding together first and second silicon oxide films on surfaces of the first and second single crystal silicon substrates. Therefore, the process of manufacture is simplified.

摘要翻译： 第一和第二单晶硅衬底通过热处理与在彼此接触的所述相应的第一和第二单晶硅衬底的表面上形成的第一和第二氧化硅膜一体化。 更具体地，通过集成形成在第一和第二单晶硅衬底上的第一和第二氧化硅膜形成绝缘区域。 由第一和第二单晶硅衬底构成的第一和第二半导体区域被绝缘区域电隔离。 结果，可以通过形成元件的第一半导体区域的影响来减小在第二半导体区域中产生的耗尽层的宽度。 形成在第二半导体区域中的背栅极区域和不形成元件的第一半导体区域基本保持相等的电位。 以这种方式，可以提高不形成任何元件的第一半导体区域与后栅极区域之间的屈服电压特性。 通过将第一和第二单晶硅基板的表面上的第一和第二氧化硅膜接合在一起，形成将第一和第二半导体区域彼此电隔离的绝缘区域。 因此，简化了制造过程。

公开(公告)号：US5008724A

公开(公告)日：1991-04-16

申请号：US547361

申请日：1990-07-03

申请人： Koji Shirai ,  Ken Kawamura

发明人： Koji Shirai ,  Ken Kawamura

IPC分类号： H01L27/08 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L27/0688 ,  H01L29/861

摘要： A semiconductor device comprising a semiconductor substrate, a field effect transistor formed in the substrate, and a diode connected to the field effect transistor and formed on the insulation film formed on the substrate. Since the diode is electrically insulated from the substrate by the insulation film, no parasitic PNPN thyristor is formed in the semiconductor substrate. Therefore, a latch-up is prevented from occurring in the semiconductor device.

公开(公告)号：US08624355B2

公开(公告)日：2014-01-07

申请号：US13526118

申请日：2012-06-18

申请人： Koji Shirai

发明人： Koji Shirai

IPC分类号： H01L29/72

CPC分类号： H01L29/6625 ,  H01L29/0619 ,  H01L29/735

摘要： A semiconductor device includes an n-type first guard ring layer provided between an emitter layer and a collector layer on a surface side of a base layer, and having a higher n-type impurity concentration than the base layer, and an n-type second guard ring layer provided between the first guard ring layer and a buried layer, connected to the first guard ring layer and the buried layer, and having a higher n-type impurity concentration than the base layer. The first guard ring layer has an n-type impurity concentration profile decreasing toward the second guard ring layer side, and the second guard ring layer has an impurity concentration profile decreasing toward the first guard ring layer side.

摘要翻译： 半导体器件包括：n型第一保护环层，设置在基极层的表面侧上的发射极层和集电极层之间，并且具有比基底层高的n型杂质浓度; n型第二保护环 保护环层设置在第一保护环层和掩埋层之间，连接到第一保护环层和掩埋层，并且具有比基底层更高的n型杂质浓度。 第一保护环层具有朝向第二保护环层侧减小的n型杂质浓度分布，并且第二保护环层具有朝向第一保护环层侧减小的杂质浓度分布。