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28 条记录 (耗时 0.029 秒)

    Interrupt controller with selectable interrupt nesting function
    21.
    发明授权
    Interrupt controller with selectable interrupt nesting function 失效
    具有可选中断嵌套功能的中断控制器

    公开(公告)号：US5410715A

    公开(公告)日：1995-04-25

    申请号：US8387

    申请日：1993-01-25

    申请人： Satomi Ishimoto ,  Osamu Matsushima ,  Masaki Nasu ,  Masahiro Nomura

    发明人： Satomi Ishimoto ,  Osamu Matsushima ,  Masaki Nasu ,  Masahiro Nomura

    IPC分类号： G06F13/26

    CPC分类号： G06F13/26

    摘要： An interrupt controller comprises a circuit for holding information obtained by designating one priority selected from a plurality of priorities for each of a plurality of interrupt requests, and a flag for indicating whether or not a nesting is allowed for an interrupt request having at least one predetermined priority of the plurality of priorities. On the basis of the priority information held in the circuit and information held in the flag, a controller operates so that when an interrupt request is generated in the course of execution of an interrupt processing having the predetermined priority, if the flag is in a first condition, the controller acknowledges the generated interrupt request only when the priority of the generated interrupt request is higher than the predetermined priority, and if the flag is in a second condition, the controller acknowledges the generated interrupt request not only when the priority of the generated interrupt request is higher than the predetermined priority, but also when the priority of the generated interrupt request is the same as the predetermined priority.

    摘要翻译： 中断控制器包括一个电路，用于保存通过指定从多个中断请求中的每一个的多个优先级中选择的一个优先级获得的信息，以及用于指示是否允许具有至少一个预定的中断请求的中断请求的嵌套的标志 优先考虑多项优先事项。 基于保持在电路中的优先级信息和保持在标志中的信息，控制器操作，使得当在执行具有预定优先级的中断处理的过程中产生中断请求时，如果该标志位于第一 条件是，只有当所产生的中断请求的优先级高于预定优先级时，控制器才确认产生的中断请求，并且如果标志处于第二状态，则控制器不仅在生成的中断请求的优先级 中断请求高于预定优先级，而且当所产生的中断请求的优先级与预定优先级相同时。

    Serial data processor capable of transferring data at a high speed
    23.
    发明授权
    Serial data processor capable of transferring data at a high speed 失效
    能够高速传输数据的串行数据处理器

    公开(公告)号：US4964141A

    公开(公告)日：1990-10-16

    申请号：US182006

    申请日：1988-04-15

    申请人： Osamu Matsushima ,  Yukio Maehashi

    发明人： Osamu Matsushima ,  Yukio Maehashi

    IPC分类号： G06F13/38 ,  G06F13/00 ,  H04L1/16 ,  H04L5/16 ,  H04L7/00 ,  H04L7/04 ,  H04L29/08

    CPC分类号： H04L7/0008 ,  H04L5/16 ,  H04L1/1692

    摘要： A serial data processor is coupled to a single data line and a single clock line for serial data transfer in synchronism with a clock signal. The data processor comprises a shift register coupled to the serial data line and operated to serially output the data in synchronism with a clock on the clock line, and an output buffer connected to receive the data serially outputted from the shift register and coupled to sequentially output the received data to the data line. This output buffer includes a push-pull driver having an output connected to the data line and an input driven by the data serially outputted from the shift register. A clock counter is coupled to receive the clock on the clock line so as to maintain the push-pull driver in an operable condition until the count value reaches a predetermined value and to bring the output of the push-pull driver into a floating condition after the count value reached a predetermined value. There is provided a data line control circuit coupled to the data line and controlled by the clock counter to bring the data line to a high level after the count value of the clock counter reaches the predetermined value.

    Shift register with dual clock inputs for receiving and sending information between I/O channels and host based on external and internal clock inputs respectively
    25.
    发明授权
    Shift register with dual clock inputs for receiving and sending information between I/O channels and host based on external and internal clock inputs respectively 失效
    具有双时钟输入的移位寄存器，分别基于外部和内部时钟输入在I / O通道和主机之间接收和发送信息

    公开(公告)号：US5381529A

    公开(公告)日：1995-01-10

    申请号：US937652

    申请日：1992-08-31

    申请人： Osamu Matsushima

    发明人： Osamu Matsushima

    IPC分类号： G06F15/78 ,  G06F13/42 ,  G06F13/20

    CPC分类号： G06F13/423

    摘要： A serial interface circuits internally provided in a microcomputer and including a shift register is provided with two sets of terminals, each set including a serial data input terminal, a serial data output terminal and a clock terminal, and the two sets of terminals am alternatively used by a serial channel selection flag. Thus, a multi-channel serial interface is realized.

    摘要翻译： 在微型计算机内部提供并包括移位寄存器的串行接口电路设置有两组终端，每组包括串行数据输入端，串行数据输出端和时钟端，并且两组终端交替使用 通过串行通道选择标志。 因此，实现了多通道串行接口。

    Information processor performing interrupt operation without saving contents of program counter
    26.
    发明授权
    Information processor performing interrupt operation without saving contents of program counter 失效
    信息处理器执行中断操作，而不保存程序计数器的内容

    公开(公告)号：US5163150A

    公开(公告)日：1992-11-10

    申请号：US691297

    申请日：1991-04-25

    申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

    发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

    IPC分类号： G06F13/32

    CPC分类号： G06F13/32

    摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

    摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行和中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新启动由中断到堆栈存储器的程序执行所必需的信息的堆栈操作。 虽然处理器可以在没有堆栈操作的情况下响应于第二模式信号执行中断操作，从而可以提供具有较少开销的改进的处理器。

    Information processor executing interruption program without saving contents of program counter
    27.
    发明授权
    Information processor executing interruption program without saving contents of program counter 失效
    信息处理器执行中断程序，而不保存程序计数器的内容

    公开(公告)号：US5036458A

    公开(公告)日：1991-07-30

    申请号：US287622

    申请日：1988-12-20

    申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

    发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

    IPC分类号： G06F13/32

    CPC分类号： G06F13/32

    摘要： An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.

    摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新执行由堆栈存储器中的中断而停止的程序所需的信息的堆栈操作。 处理器可以在不进行堆栈操作的情况下响应于第二模式信号执行中断操作，从而提供具有较少开销的改进的处理器。 在多种应用中描述了两种中断模式技术，包括D / A转换，串行数据传输和接收以及计算机外围设备的操作。