公开(公告)号：US5471427A

公开(公告)日：1995-11-28

申请号：US262755

申请日：1994-06-20

申请人： Shuji Murakami ,  Tomohisa Wada ,  Kenji Anami

发明人： Shuji Murakami ,  Tomohisa Wada ,  Kenji Anami

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/848

摘要： A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and nor program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.

摘要翻译： 在行或列解码器和存储单元阵列之间提供用于修复有缺陷的存储单元的电路。 当解码器具有n条输出线时，存储单元阵列至少包括（N + 1）行或列线，其中n是整数。 修复电路包括用于将解码器的输出线连接到行或列线的连接电路，以及用于限定连接电路的连接的电路。 连接电路包括n个开关元件，每个开关元件可操作以将解码器的一个输出线连接到至少两个行或列线。 定义电路定义每个开关元件的连接路径，使得解码器的输出线与连续有缺陷的存储器单元的行或列线排除在连续定位的行或列之间一一对应。 定义电路包括设置在工作电压源和接地线之间的一系列激光可编程保险丝元件。 由于没有备用解码器和编程电路，修复电路占用了芯片的减少面积，并且由于要被熔断的熔丝元件的数量减少，所以它进行可靠且快速的存储器修复。

公开(公告)号：US5379258A

公开(公告)日：1995-01-03

申请号：US828254

申请日：1992-01-30

申请人： Shuji Murakami ,  Tomohisa Wada ,  Kenji Anami

发明人： Shuji Murakami ,  Tomohisa Wada ,  Kenji Anami

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/848 ,  G11C29/70

摘要： A circuit for repairing a defective memory cell between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and no program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.

摘要翻译： 一种用于修复行或列解码器和存储单元阵列之间的有缺陷的存储单元的电路。 当解码器具有n条输出线时，存储单元阵列至少包括（N + 1）行或列线，其中n是整数。 修复电路包括用于将解码器的输出线连接到行或列线的连接电路和用于限定连接电路的连接的电路。 连接电路包括n个开关元件，每个开关元件可操作以将解码器的一个输出线连接到至少两个行或列线。 定义电路定义每个开关元件的连接路径，使得解码器的输出线与连续有缺陷的存储器单元的行或列线排除在连续定位的行或列之间一一对应。 定义电路包括设置在工作电压源和接地线之间的一系列激光可编程保险丝元件。 由于没有备用解码器和编程电路，修复电路占用了芯片的减少面积，并且由于要被熔断的熔丝元件的数量减少，所以其执行可靠且快速的存储器修复。

公开(公告)号：US5282175A

公开(公告)日：1994-01-25

申请号：US705817

申请日：1991-05-24

申请人： Koreaki Fujita ,  Shuji Murakami ,  Kenji Anami

发明人： Koreaki Fujita ,  Shuji Murakami ,  Kenji Anami

IPC分类号： G11C11/418 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/41

CPC分类号： G11C8/14 ,  G11C8/12

摘要： In a SRAM of a selected word line structure, each local decoder is connected to a corresponding main word line and a corresponding Z decoder signal line. Each local decoder includes a circuit including two MOS transistors connected in series to each other which circuit has one end grounded. The corresponding local word line is connected to a node between these two transistors. Out of the corresponding main word line and the corresponding Z decoder signal line, one is connected to the gates of these transistors and the other is connected to the other end of said circuit, which the other end is not grounded. The potential on the corresponding local word line attains a high level only when the potential on the signal line connected to the gate of these two transistors, is at a logical level at which the transistor can be turned on and the potential on said one signal line is at a high level. Theoretically, therefore, each local word line is controlled to be activated or inactivated by the operations of two elements in the corresponding local decoder.

摘要翻译： 在所选字线结构的SRAM中，每个本地解码器连接到对应的主字线和对应的Z解码器信号线。 每个本地解码器包括一个包括彼此串联连接的两个MOS晶体管的电路，该电路具有一端接地。 相应的本地字线连接到这两个晶体管之间的节点。 在相应的主字线和相应的Z解码器信号线之外，一个连接到这些晶体管的栅极，另一个连接到另一端不接地的所述电路的另一端。 只有当连接到这两个晶体管的栅极的信号线上的电位处于晶体管可以导通的逻辑电平并且所述一个信号线上的电位时，相应本地字线上的电位才达到高电平 处于高水平。 因此，理论上，每个局部字线被相应的本地解码器中的两个元件的操作控制为被激活或失活。

公开(公告)号：US5276652A

公开(公告)日：1994-01-04

申请号：US943648

申请日：1992-09-11

申请人： Kenji Anami

发明人： Kenji Anami

IPC分类号： G11C11/413 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C11/34

CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C11/418

摘要： A static random access memory includes a plurality of memory cells each constituted by 5 elements. One memory cell is connected to a single bit line through a single access gate transistor. Additionally, a source line potential controlling circuit is provided for applying a predetermined intermediate potential to the source of a driver transistor of the memory cell in a column which is not accessed, when the memory cell is not accessed. Since one memory cell is constituted by only five elements, and connected to a single bit line, its density is improved. Furthermore, since a power supply voltage applied to the memory cell provided in the column which is not accessed is decreased by an effect of a source line potential controlling circuit, power consumption is decreased, and moreover, destruction of the memory cell can be prevented.

摘要翻译： 静态随机存取存储器包括由5个元件构成的多个存储单元。 一个存储单元通过单个存取栅极晶体管连接到单个位线。 此外，提供源极线电位控制电路，用于当未访问存储器单元时，在未访问的列中将预定中间电位施加到存储器单元的驱动晶体管的源极。 由于一个存储单元仅由五个元件构成，并且连接到单个位线，所以其密度提高。 此外，由于通过源极线电位控制电路的作用，施加到设置在未访问的列中的存储单元的电源电压降低，因此功耗降低，此外可以防止存储单元的破坏。

公开(公告)号：USRE33280E

公开(公告)日：1990-07-31

申请号：US123106

申请日：1987-11-19

申请人： Masahiko Yoshimoto ,  Tsutomu Yoshihara ,  Kenji Anami ,  Hirofumi Shinohara

发明人： Masahiko Yoshimoto ,  Tsutomu Yoshihara ,  Kenji Anami ,  Hirofumi Shinohara

IPC分类号： G11C5/06 ,  G11C8/14

CPC分类号： G11C5/063 ,  G11C8/14

摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.

公开(公告)号：US4910425A

公开(公告)日：1990-03-20

申请号：US236725

申请日：1988-08-26

申请人： Atsushi Ohba ,  Kenji Anami

发明人： Atsushi Ohba ,  Kenji Anami

IPC分类号： H03K19/003 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/00376

摘要： When an input terminal, which is connected to an input transistor, is opened, a transistor having an emitter connected to the input transistor conducts to supply constant current to a constant current source which is connected to the emitter of the input transistor. Therefore, load current of a reference circuit connected to the constant current source is not changed even if the input terminal is opened. As the result, current values of all constant current sources receiving voltage from the reference circuit are not changed so that the internal circuit of a semiconductor integrated circuit device can be stably operated.

摘要翻译： 当连接到输入晶体管的输入端被打开时，具有连接到输入晶体管的发射极的晶体管导通，以向连接到输入晶体管的发射极的恒定电流源提供恒定电流。 因此，连接到恒流源的参考电路的负载电流即使输入端子打开也不会改变。 结果，从参考电路接收电压的所有恒定电流源的电流值不改变，从而可以稳定地操作半导体集成电路器件的内部电路。

公开(公告)号：US4907203A

公开(公告)日：1990-03-06

申请号：US264189

申请日：1988-10-31

申请人： Tomohisa Wada ,  Kenji Anami

发明人： Tomohisa Wada ,  Kenji Anami

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/418 ,  G11C29/00 ,  G11C29/34 ,  G11C29/56

CPC分类号： G11C11/418

摘要： A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, a plurality of sense amplifiers, a plurality of write circuits, a signal switching circuit, a plurality of input buffers, a plurality of output buffers and a plurality of terminals, which are formed on the same chip. A switching signal B1/B4 is applied to one of the plurality of terminals. The semiconductor memory device has a 256K word by 4 bit organization when the switching signal B1/B4 is at an "L" level and has a 1M word by 1 bit organization when the switching signal B1/B4 is at an "H" level. The word organization can be switched mainly by the signal switching circuit.

摘要翻译： 半导体存储器件包括存储单元阵列，行解码器，列解码器，多个读出放大器，多个写入电路，信号切换电路，多个输入缓冲器，多个输出缓冲器和多个 端子，形成在同一芯片上。 切换信号B1 / B4被施加到多个终端中的一个。 当切换信号B1 / B4处于“H”电平时，当切换信号B1 / B4处于“L”电平并具有1M字1位组织时，半导体存储器件具有256K字4位组织。 单词组织主要由信号切换电路切换。

公开(公告)号：US4792923A

公开(公告)日：1988-12-20

申请号：US901745

申请日：1986-08-29

申请人： Yasunobu Nakase ,  Kenji Anami

发明人： Yasunobu Nakase ,  Kenji Anami

IPC分类号： G11C5/00 ,  G11C11/411 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C5/005 ,  G11C11/4116 ,  G11C11/415

摘要： A semiconductor memory device having a plurality of word line pairs and drain lines, a plurality of bit line pairs, and a plurality of memory cells connected to both of the word line pairs and the bit line pairs at the cross points thereof, comprising: a first and a second word line provided as the word line pair, a memory cell including a first and a second multi-emitter transistor whose commonly connected emitters are connected to the drain line, first and second resistors where one of their ends are connected between the collectors of the first and second multi-emitter transistors respectively, and where their other ends are both connected to the first word line and the bases of the second and first multi-emitter transistors are connected to the other's collectors, respectively, and first and second diodes such as Schottky barrier diodes are connected between the collectors of the first and second multi-emitter transistors and the second word line, respectively. A current which is provided for each row which consists of an input transistor which receives an address input signal at its base input and a reference transistor which receives a predetermined voltage at its base input with the emitters thereof being commonly connected with each other. Third and fourth resistors are serially connected between the collector of the input transistor and a power supply voltage. A first word line driving transistor for driving the first word line whose base is connected between the third resistor and the fourth resistor and whose emitter is connected to the first word line. A second word line driving transistor for driving the second word line whose base is connected between the collector of the input transistor and the fourth resistor and whose emitter is connected to the second word line. The collectors of the first and the second word line driving transistor are connected to the voltage power supply.

摘要翻译： 一种半导体存储器件，具有多个字线对和漏极线，多个位线对和连接到其交叉点处的字线对和位线对的多个存储单元，包括： 设置为字线对的第一和第二字线;存储单元，包括共同连接的发射极连接到漏极线的第一和第二多发射极晶体管，第一和第二电阻的一端连接在漏极线之间 第一和第二多发射极晶体管的集电极分别连接到第一字线，第二和第二多发射极晶体管的基极分别连接到另一个集电极，第一和第二 诸如肖特基势垒二极管的二极管分别连接在第一和第二多发射极晶体管和第二字线的集电极之间。 为每行提供的电流由输入晶体管构成，该输入晶体管在其基极输入端接收地址输入信号，而基准晶体管在其基极输入端接收与其发射极的预定电压相互共同连接。 第三和第四电阻串联连接在输入晶体管的集电极和电源电压之间。 第一字线驱动晶体管，用于驱动第一字线，其基极连接在第三电阻和第四电阻之间，其发射极连接到第一字线。 第二字线驱动晶体管，用于驱动第二字线，其基极连接在输入晶体管的集电极和第四电阻之间，其发射极连接到第二字线。 第一和第二字线驱动晶体管的集电极连接到电压电源。

公开(公告)号：US4791382A

公开(公告)日：1988-12-13

申请号：US156433

申请日：1988-02-16

申请人： Toru Shiomi ,  Kenji Anami

发明人： Toru Shiomi ,  Kenji Anami

IPC分类号： G11C11/407 ,  G11C11/41 ,  G11C11/415 ,  H03F3/18 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03K17/567 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944 ,  H03F3/16

CPC分类号： H03K17/567 ,  H03K19/09448

摘要： A driver circuit comprises a bipolar transistor for passing current from a power supply potential V.sub.CC to an output terminal, two CMOS inverters connected between an input terminal and the output terminal, a diode for passing current from the output terminal to the input terminal, and an NMOSFET for passing current from the input terminal to a power supply potential V.sub.EE. When a signal applied to the input terminal falls from an "H" level to an "L" level, the potential of the output terminal is changed from V.sub.CC to V.sub.EE. At the time, current flows from the output terminal to the input terminal through the diode. In addition, the current flows to the power supply potential V.sub.EE through the NMOSFET. When the signal applied to the input terminal rises from the "L" level to the "H" level, the potential of the output terminal is changed from the V.sub.EE to the V.sub.CC. At that time, current flows from the power supply potential V.sub.CC to the output terminal through the bipolar transistor.

摘要翻译： 驱动器电路包括用于将电流从电源电位VCC传递到输出端子的双极晶体管，连接在输入端子和输出端子之间的两个CMOS反相器，用于将电流从输出端子传递到输入端子的二极管，以及 用于将电流从输入端子传递到电源电位VEE的NMOSFET。 当施加到输入端子的信号从“H”电平降低到“L”电平时，输出端子的电位从VCC变为VEE。 此时，电流通过二极管从输出端流向输入端。 此外，电流通过NMOSFET流向电源电位VEE。 当施加到输入端子的信号从“L”电平上升到“H”电平时，输出端子的电位从VEE变为VCC。 此时，电流通过双极晶体管从电源电位VCC流向输出端子。

公开(公告)号：US4772930A

公开(公告)日：1988-09-20

申请号：US48509

申请日：1987-05-04

申请人： Kenji Anami ,  Masahiko Yoshimoto ,  Satoru Kamoto

发明人： Kenji Anami ,  Masahiko Yoshimoto ,  Satoru Kamoto

IPC分类号： H01L27/08 ,  H01L21/74 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L27/02

CPC分类号： H01L27/0921 ,  H01L21/743 ,  H01L23/5286 ,  H01L23/535 ,  H01L2924/0002

摘要： A power supply voltage to be applied to a metallic connection 36a is supplied through an n.sup.+ diffusion region 34a, an N type well 22, an n.sup.+ diffusion region 34c and a metallic connection 36C to a p.sup.+ diffusion region 23b serving as a power supply line. An n.sup.+ diffusion region 73 serving as a ground line is grounded through a metallic connection 76c, a p.sup.+ diffusion region 74c, a P type well 72, a p.sup.+ diffusion region 74b and a metallic connection 76b.

摘要翻译： 施加到金属连接36a的电源电压通过n +扩散区域34a，N型阱22，n +扩散区域34c和金属连接件36C提供给用作电源线的p +扩散区域23b。 用作接地线的n +扩散区73通过金属连接76c，p +扩散区74c，P型阱72，p +扩散区74b和金属连接76b接地。