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公开(公告)号：USRE33280E
公开(公告)日：1990-07-31
申请号：US123106
申请日：1987-11-19
摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.
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公开(公告)号：US4554646A
公开(公告)日：1985-11-19
申请号：US542388
申请日：1983-10-17
摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.
摘要翻译： 存储器矩阵在列的方向上分割成多组存储器单元。 存储器单元可以通过各自的前面的字线访问，每个字线是为矩阵的每一行提供的，并且通常是存储器单元的所有组以及每个组和每行提供的组字线，因此 在访问时间期间仅在属于包括要访问的特定存储器的特定组的列中建立列电流的路径。
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公开(公告)号：USRE32993E
公开(公告)日：1989-07-18
申请号：US97770
申请日：1987-09-17
摘要： A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines flow resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.
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公开(公告)号：US4521704A
公开(公告)日：1985-06-04
申请号：US462204
申请日：1983-01-31
IPC分类号： G11C11/417 , H03F3/26 , H03F3/45 , H03K5/02
CPC分类号： H03F3/265 , H03F3/45076 , H03F2203/45318 , H03F2203/45394
摘要： A differential amplifying circuit includes a pair of main amplifying circuits (5a, 5b) each having at least three input terminals and at least one output terminal, and a pair of auxiliary amplifying circuits (6a, 6b) each having at least one input terminal. Complimentary inputs (D1, D1) are connected to the input terminals of said pair of auxiliary amplifying circuits (6a, 6b), the outputs (D2, D2) of the main amplifying circuits (5a, 5b) are connected as crossing feedback inputs to at least a pair of input terminals of said pair of main amplifying circuits (5a, 5b), the complimentary inputs (D2, D2) are also connected to the other at least one pair of input terminals, and the outputs of said auxiliary amplifying circuits (6a, 6b) are further connected to the further at least pair of input terminals.
摘要翻译： 差分放大电路包括一对主放大电路（5a，5b），每一个具有至少三个输入端和至少一个输出端，以及一对辅助放大电路（6a，6b），每一个具有至少一个输入端。 免费输入（D1，＆amp; upbar＆D）连接到所述一对辅助放大电路（6a，6b）的输入端，主放大电路（5a，5b）的输出（D2，＆amp; upbar＆D） 输入到所述一对主放大电路（5a，5b）中的至少一对输入端，所述互补输入（D2，＆amp;上和下）也连接到另一个至少一对输入端，并且所述输出 辅助放大电路（6a，6b）进一步连接到另外的至少一对输入端。
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公开(公告)号：US4542486A
公开(公告)日：1985-09-17
申请号：US500608
申请日：1983-06-02
摘要： A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines of low resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.
摘要翻译： 通过将存储单元划分成多个电容器组并提供组选择线，半导体存储器件关于电流消耗和存取时间被改进。 低电阻的前端字线连接到行解码器的输出，与门接收组选择线上的选择信号和前端字线的输出。 长度相对较短的字线连接到AND输出。
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6.发明申请SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权半导体集成电路装置及制造半导体集成电路装置的方法公开(公告)号：US20140035055A1
公开(公告)日：2014-02-06
申请号：US14111549
申请日：2012-04-09
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L27/088 , H01L21/823842 , H01L21/823878 , H01L29/66477
摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。 这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。 因此，通过在High-k栅极绝缘膜上形成各种阈值电压调整金属膜并将膜分量从它们引入到高k栅极绝缘膜中来控制阈值电压。 然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。 根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。
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公开(公告)号：US08269288B2
公开(公告)日：2012-09-18
申请号：US12253563
申请日：2008-10-17
申请人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
发明人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
IPC分类号： H01L29/06
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/28035 , H01L21/3081 , H01L21/3086 , H01L21/321 , H01L29/785
摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
摘要翻译： 本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。 本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极， 翅片状半导体部分，其间具有栅极绝缘膜。 解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。
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8.发明授权Machining method, program, machining-program generating program and machining apparatus of press die 有权加工方法，程序，加工程序生成程序和压模加工装置公开(公告)号：US08137038B2
公开(公告)日：2012-03-20
申请号：US12276441
申请日：2008-11-24
CPC分类号： B23C3/00 , B23C2220/56 , G05B19/4097 , Y10T409/300896 , Y10T409/303808 , Y10T409/304144 , Y10T409/307056 , Y10T409/308288 , Y10T409/30868 , Y10T483/1795
摘要： A machining method of a press die having a pierce cutter and a secondary relief-clearance area recessed inward relative to a profile of the pierce cutter is provided. A plunge cutting tool having a tool body and at least one edge portion provided on an outer circumference of an end of the tool body is used, the edge portion being protruding from the outer circumference of the tool body and being capable of carving while rotating around an axis of the tool body and moving in an axial direction of the tool body. While rotating the plunge cutting tool with an axis of the tool body being approximately parallel to a surface of the pierce cutter, the plunge cutting tool is relatively moved along the profile of the pierce cutter. The plunge cutting tool is also relatively moved in the axial direction of the tool body along the shape of the pierce cutter and the secondary relief-clearance area in a piercing direction each time the plunge cutting tool is relatively moved by a predetermined pitch.
摘要翻译： 提供了一种具有穿孔切割器和相对于穿孔刀的轮廓向内凹入的副卸压间隙区域的冲压模具的加工方法。 使用具有工具主体和设置在工具主体的端部的外周上的至少一个边缘部分的插入切削工具，该边缘部分从工具主体的外周突出并且能够在旋转周围进行雕刻 工具主体的轴线并沿着工具主体的轴向方向移动。 当刀具本体的轴线大致平行于穿孔刀的表面旋转插入式切割工具时，插入式切割工具沿着穿孔刀的轮廓相对移动。 每当插入式切削工具以预定的间距相对移动时，插入式切削工具也沿着穿孔刀具的形状沿着穿孔方向相对移动，并且在穿孔方向上相对移动。
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公开(公告)号：US06245603B1
公开(公告)日：2001-06-12
申请号：US09498069
申请日：2000-02-04
申请人： Hirofumi Shinohara
发明人： Hirofumi Shinohara
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L29/1083 , H01L29/6659
摘要： A manufacturing method for a semiconductor device permits a MOSFET with a pocket layer to be securely formed even when microminiaturization makes it difficult to implant impurity ions at an angle with respect to a silicon substrate in manufacturing a semiconductor, a MOSFET having a pocket layer in particular. A gate electrode composed of a gate oxide film, a poly-silicon, and a tungsten silicide, and a nitride film pattern are selectively formed on a p-type silicon substrate, then p-type impurity ions are implanted perpendicularly to the p-type silicon substrate. A p-type ion implantation region formed by implanting the p-type impurity ions is diffused for activation to thereby form a pocket layer before another ion implantation region is formed.
摘要翻译： 半导体器件的制造方法允许具有袋层的MOSFET即使在制造半导体时微小化使得难以相对于硅衬底以一定角度注入杂质离子，特别是具有袋层的MOSFET也可以牢固地形成 。 在p型硅衬底上选择性地形成由栅极氧化膜，多晶硅和硅化钨构成的栅电极和氮化物膜图案，然后将p型杂质离子垂直于p型 硅衬底。 通过注入p型杂质离子形成的p型离子注入区域被扩散用于激活，从而在形成另一个离子注入区域之前形成袋层。
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公开(公告)号：US5394338A
公开(公告)日：1995-02-28
申请号：US805139
申请日：1991-12-11
CPC分类号： G06F17/5068
摘要： A module cell generating device of a semiconductor integrated circuit includes a parameter input part for applying a designation parameter, a basic cell group storing the basic cells, and a basic cell arranging and wiring process part for generating layout designing data by utilizing a structure description part which is a control description for defining the arrangement method and the wiring method of the basic cells, the designation parameter, the structure description, and the basic cells. Furthermore, it includes a basic cell generating process part for generating the newly designated basic cells in accordance with the designation parameter.
摘要翻译： 半导体集成电路的模块单元产生装置包括用于应用指定参数的参数输入部分，存储基本单元的基本单元组，以及用于通过利用结构描述部分来生成布局设计数据的基本单元布置和布线处理部分 这是用于定义基本单元的布置方法和布线方法的控制描述，指定参数，结构描述和基本单元。 此外，它包括用于根据指定参数生成新指定的基本单元的基本单元产生处理部分。
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