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21.发明授权Communicating between partitions in a statically partitioned multiprocessing system 有权在静态分区的多处理系统中的分区之间进行通信公开(公告)号：US07882327B2
公开(公告)日：2011-02-01
申请号：US11831102
申请日：2007-07-31
IPC分类号： G06F12/02
CPC分类号： G06F15/17
摘要： In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.
摘要翻译： 在一个实施例中，一种方法包括向系统的第一分区中的第一多个节点和系统的第二分区中的第二多个节点中的每一个分配唯一的节点号。 第一存储器地址空间跨越包括在第一分区中的第一存储器，并且第二存储器地址空间跨越包括在第二分区中的第二存储器。 第一存储器地址空间和第二存储器地址空间通常在逻辑上是不同的。 该方法还包括编程第一分区中的第一地址映射以将第一存储器地址空间映射到节点号，其中编程包括将第一存储器地址空间内的第一存储器地址范围映射到分配给第一节点的第一节点号 的第二分区中的第二多个节点，由此第一存储器地址范围被映射到第二分区。
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公开(公告)号：US20090106498A1
公开(公告)日：2009-04-23
申请号：US11877311
申请日：2007-10-23
申请人： Kevin Michael Lepak , Gregory William Smaus , William A. Hughes , Vydhyanathan Kalyanasundharam
发明人： Kevin Michael Lepak , Gregory William Smaus , William A. Hughes , Vydhyanathan Kalyanasundharam
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F12/0815
摘要： A system and method for obtaining coherence permission for speculative prefetched data. A memory controller stores an address of a prefetch memory line in a prefetch buffer. Upon allocation of an entry in the prefetch buffer a snoop of all the caches in the system occurs. Coherency permission information is stored in the prefetch buffer. The corresponding prefetch data may be stored elsewhere. During a subsequent memory access request for a memory address stored in the prefetch buffer, both the coherency information and prefetched data may be already available and the memory access latency is reduced.
摘要翻译： 一种用于获取推测预取数据的一致性许可的系统和方法。 存储器控制器将预取存储器行的地址存储在预取缓冲器中。 在预取缓冲区中分配条目后，会发生系统中所有缓存的窥探。 一致性许可信息存储在预取缓冲区中。 相应的预取数据可以存储在别处。 在存储在预取缓冲器中的存储器地址的后续存储器访问请求期间，一致性信息和预取数据可能已经可用，并且存储器访问等待时间减少。
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公开(公告)号：US07877558B2
公开(公告)日：2011-01-25
申请号：US11837943
申请日：2007-08-13
CPC分类号： G06F13/1626
摘要： A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.
摘要翻译： 系统包括通过存储器控制器耦合到存储器的处理器。 存储器控制器包括第一和第二队列。 存储器控制器从处理器接收存储器请求，为每个请求分配优先级，将每个请求存储在第一个队列中，并根据其优先级对请求进行调度处理。 存储器控制器响应于触发器改变第一队列中的请求的优先级，响应于检测到下一个调度的请求而将下一个调度的请求从第一队列发送到第二队列，该请求具有第一队列中的任何请求的最高优先级 队列，并将请求从第二个队列发送到内存。 内存控制器根据不同类型的触发器更改不同类型请求的优先级。 存储器控制器维护发送到第一队列中的第二队列的每个请求的副本。
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公开(公告)号：US07840780B2
公开(公告)日：2010-11-23
申请号：US12098303
申请日：2008-04-04
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F9/00
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译： 在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。 节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。 在另一个实施例中，节点包括处理器核心和节点控制器。 节点控制器包括由处理器核共享的队列。 处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。 在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。 在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。
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公开(公告)号：US20080184009A1
公开(公告)日：2008-07-31
申请号：US12098303
申请日：2008-04-04
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译： 在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。 节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。 在另一个实施例中，节点包括处理器核心和节点控制器。 节点控制器包括由处理器核共享的队列。 处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。 在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。 在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。
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26.发明授权公开(公告)号：US07328371B1
公开(公告)日：2008-02-05
申请号：US10966466
申请日：2004-10-15
申请人： Vydhyanathan Kalyanasundharam , William A. Hughes , Philip E. Madrid , Scott A. White , Ajay Naini
发明人： Vydhyanathan Kalyanasundharam , William A. Hughes , Philip E. Madrid , Scott A. White , Ajay Naini
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1679 , G06F11/181 , G06F11/184 , G06F2201/845
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller coupled to the processor cores. The node controller is configured to route communications from the processor cores to other devices in a computer system. The node controller comprises a circuit coupled to receive the communications from the processor cores. In a redundant execution mode in which at least a first processor core is redundantly executing code that a second processor core is also executing, the circuit is configured to compare communications from the first processor core to communications from the second processor core to verify correct execution of the code. In some embodiments, the processor cores and the node controller may be integrated onto a single integrated circuit chip as a CMP. A similar method is also contemplated.
摘要翻译： 在一个实施例中，节点包括多个处理器核和耦合到处理器核的节点控制器。 节点控制器被配置为将来自处理器核心的通信路由到计算机系统中的其他设备。 节点控制器包括耦合以从处理器核心接收通信的电路。 在冗余执行模式中，其中至少第一处理器核冗余地执行第二处理器核也正在执行的代码，该电路被配置为将来自第一处理器核心的通信与来自第二处理器核心的通信进行比较，以验证是否正确执行 代码。 在一些实施例中，处理器核心和节点控制器可以作为CMP集成到单个集成电路芯片上。 也可以考虑类似的方法。
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公开(公告)号：US20120155273A1
公开(公告)日：2012-06-21
申请号：US12968857
申请日：2010-12-15
IPC分类号： H04L12/26
CPC分类号： G06F15/17312
摘要： A multi-chip module configuration includes two processors, each having two nodes, each node including multiple cores or compute units. Each node is connected to the other nodes by links that are high bandwidth or low bandwidth. Routing of traffic between the nodes is controlled at each node according to a routing table and/or a control register that optimize bandwidth usage and traffic congestion control.
摘要翻译： 多芯片模块配置包括两个处理器，每个处理器具有两个节点，每个节点包括多个核心或计算单元。 每个节点通过高带宽或低带宽的链路连接到其他节点。 根据路由表和/或优化带宽使用和业务拥塞控制的控制寄存器，在每个节点处控制节点之间的业务路由。
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公开(公告)号：US20130024829A1
公开(公告)日：2013-01-24
申请号：US13184982
申请日：2011-07-18
申请人： Benjamin Tsien , Kiran Bondalapati , Hao Huang , William A. Hughes , Eric Rentschler , Jeremy Schreiber , Aaron J. Grenat
发明人： Benjamin Tsien , Kiran Bondalapati , Hao Huang , William A. Hughes , Eric Rentschler , Jeremy Schreiber , Aaron J. Grenat
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31705 , G06F2217/78
摘要： Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.
摘要翻译： 描述了在电源门控序列期间分析和校正在电路工作中发生的故障的电路和方法。 该方法包括执行包括维持跟踪捕获缓冲器（TCB）的操作的电源门控序列的修改; 在TCB中记录执行期间发生的事件; 并根据对TCB记录事件的分析来纠正故障。 该电路包括多个包括TCB的部件和被配置为在第一状态下保持对TCB的电源并且在第二状态下关闭到TCB的电源的开关。
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公开(公告)号：US08595563B2
公开(公告)日：2013-11-26
申请号：US13184982
申请日：2011-07-18
申请人： Benjamin Tsien , Kiran Bondalapati , Hao Huang , William A. Hughes , Eric Rentschler , Jeremy Schreiber , Aaron J. Grenat
发明人： Benjamin Tsien , Kiran Bondalapati , Hao Huang , William A. Hughes , Eric Rentschler , Jeremy Schreiber , Aaron J. Grenat
IPC分类号： G06F11/00
CPC分类号： G06F17/505 , G01R31/31705 , G06F2217/78
摘要： Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.
摘要翻译： 描述了在电源门控序列期间分析和校正在电路工作中发生的故障的电路和方法。 该方法包括执行包括维持跟踪捕获缓冲器（TCB）的操作的电源门控序列的修改; 在TCB中记录执行期间发生的事件; 并根据对TCB记录事件的分析来纠正故障。 该电路包括多个包括TCB的部件和被配置为在第一状态下保持对TCB的电源并且在第二状态下关闭到TCB的电源的开关。
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公开(公告)号：US08787368B2
公开(公告)日：2014-07-22
申请号：US12961884
申请日：2010-12-07
CPC分类号： H04L49/101 , G06F13/1657 , H04L49/10 , H04L49/1576
摘要： A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.
摘要翻译： 本文描述了具有主要和次要选择器的交叉开关。 交叉开关包括交叉开关命令调度器，其调度将跨越交叉开关从多个源端口路由到多个目的地端口的命令。 交叉开关命令调度器使用主选择器和辅助选择器在每个时钟周期调度两个命令。 交叉开关还可以包括专用响应总线，通用总线和专用命令总线。 系统请求接口可以包括专用命令和数据分组缓冲器以与主要和辅助选择器一起工作。
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