公开(公告)号：US20210294519A1

公开(公告)日：2021-09-23

申请号：US17010002

申请日：2020-09-02

Applicant: Kioxia Corporation

Inventor： Sai CHANDRA TEJA RADHAPURAM ,  Marie TAKADA

IPC: G06F3/06

Abstract: A memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of non-volatile memory dies. The controller controls the non-volatile memory. The controller manages the history of a command issued to the non-volatile memory for each of the plurality of non-volatile memory dies, and when a read command directed to a first non-volatile memory die among the plurality of non-volatile memory dies is issued, predicts the temperature of the first non-volatile memory die based on the history of the command, and applies a voltage to the first non-volatile memory die to read the target data of the read command based on the predicted temperature.

公开(公告)号：US20210089392A1

公开(公告)日：2021-03-25

申请号：US16807220

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA ,  Ryo YAMAKI ,  Osamu TORII ,  Naomi TAKEDA

IPC: G06F11/10 ,  G06F9/30

Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

公开(公告)号：US20250004880A1

公开(公告)日：2025-01-02

申请号：US18882152

申请日：2024-09-11

Applicant: KIOXIA CORPORATION

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

公开(公告)号：US20240363174A1

公开(公告)日：2024-10-31

申请号：US18768178

申请日：2024-07-10

Applicant: KIOXIA CORPORATION

Inventor： Masanobu SHIRAKAWA ,  Tsukasa TOKUTOMI ,  Marie TAKADA

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/26 ,  G11C11/5671 ,  G11C16/0483 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

公开(公告)号：US20240312519A1

公开(公告)日：2024-09-19

申请号：US18666886

申请日：2024-05-17

Applicant: KIOXIA CORPORATION

Inventor： Tomonori TAKAHASHI ,  Masanobu SHIRAKAWA ,  Osamu TORII ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

公开(公告)号：US20240094957A1

公开(公告)日：2024-03-21

申请号：US18522343

申请日：2023-11-29

Applicant: KIOXIA CORPORATION

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA ,  Tsukasa TOKUTOMI

IPC: G06F3/06 ,  G06F11/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/52

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/52 ,  G11C11/5671

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

公开(公告)号：US20240021250A1

公开(公告)日：2024-01-18

申请号：US18362221

申请日：2023-07-31

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Shohei ASAMI ,  Masamichi FUJIWARA

IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/08

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

公开(公告)号：US20220093199A1

公开(公告)日：2022-03-24

申请号：US17202432

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA

IPC: G11C29/42 ,  G11C29/20 ,  G11C29/12

Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.

公开(公告)号：US20220028460A1

公开(公告)日：2022-01-27

申请号：US17202627

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA

IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.

公开(公告)号：US20230420067A1

公开(公告)日：2023-12-28

申请号：US18053896

申请日：2022-11-09

Applicant: Kioxia Corporation

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Ryo YAMAKI

IPC: G11C29/52 ,  G11C11/4096 ,  G11C11/4074

CPC classification number: G11C29/52 ,  G11C11/4096 ,  G11C11/4074

Abstract: A memory system includes a nonvolatile memory including memory cells each configured to store first and second bits, and a memory controller. The memory controller is configured to: read first data by using a first voltage to a first read process that reads data corresponding to the first bit from the memory cells; read second data by using a second voltage to a second read process that reads data corresponding to the second bit from the memory cells; in a case where an error correction process of the first data is successful, determine a third voltage, based on the first data and third data that is obtained by error-correcting the first data; and update a first read voltage that is used to the first read process, from the first voltage to the third voltage.