DRY ETCH POLYSILICON REMOVAL FOR REPLACEMENT GATES
    21.
    发明申请
    DRY ETCH POLYSILICON REMOVAL FOR REPLACEMENT GATES 有权
    用于替换盖的干燥多晶硅去除

    公开(公告)号:US20130217221A1

    公开(公告)日:2013-08-22

    申请号:US13398991

    申请日:2012-02-17

    IPC分类号: H01L21/28

    摘要: Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

    摘要翻译: 半导体器件形成有最后的高K /金属栅极工艺,完全去除多晶硅虚拟栅极并且具有用于金属填充物的低纵横比的间隙。 实施例包括在基板上形成虚拟栅电极,虚拟栅电极具有氮化物盖,在虚拟栅电极的相对侧上形成隔板,在其间形成栅极沟槽,干蚀刻氮化物盖,使栅极沟槽顶角逐渐变细; 在虚拟栅电极的一部分上进行选择性干蚀刻,并湿法蚀刻伪栅电极的其余部分。

    Methods for fabricating integrated circuits with controlled P-channel threshold voltage
    23.
    发明授权
    Methods for fabricating integrated circuits with controlled P-channel threshold voltage 有权
    用于制造具有受控P沟道阈值电压的集成电路的方法

    公开(公告)号:US08420519B1

    公开(公告)日:2013-04-16

    申请号:US13286292

    申请日:2011-11-01

    IPC分类号: H01L21/283

    摘要: Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the gate dielectric. A sub-monolayer of tantalum oxide is deposited overlying the layer of tantalum nitride by a process of atomic layer deposition, and oxygen is diffused from the tantalum oxide through the tantalum nitride and titanium nitride.

    摘要翻译: 提供了用于制造具有受控阈值电压的集成电路的方法。 根据一个实施例,一种方法包括形成覆盖在N掺杂硅衬底上的栅极电介质,并且沉积氮化钛层和覆盖在栅极电介质上的氮化钽层。 氧化钽的亚单层通过原子层沉积的过程沉积在氮化钽层上,并且氧从钽氧化物扩散通过氮化钽和氮化钛。

    HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY REDUCING A GATE FILL ASPECT RATIO IN REPLACEMENT GATE TECHNOLOGY
    24.
    发明申请
    HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY REDUCING A GATE FILL ASPECT RATIO IN REPLACEMENT GATE TECHNOLOGY 有权
    通过减少门盖技术中的门盖填充比例而形成的高K金属电极结构

    公开(公告)号:US20120319205A1

    公开(公告)日:2012-12-20

    申请号:US13489539

    申请日:2012-06-06

    IPC分类号: H01L21/28 H01L27/088

    CPC分类号: H01L21/823842

    摘要: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity.

    摘要翻译: 当在更换栅极方法的基础上形成复杂的高k金属栅电极结构时,填充高导电电极金属(例如铝)时的填充条件可以通过去除最终功函数金属的上部来增强, 例如P沟道晶体管中的氮化钛材料。 在一些说明性实施例中,可以在门开口的上部中选择性地去除含金属的电极材料,而不会过度增加整个工艺的复杂性。

    HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS USING A MASKING REGIME PRIOR TO GATE PATTERNING
    26.
    发明申请
    HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS USING A MASKING REGIME PRIOR TO GATE PATTERNING 有权
    高K金属电极结构通过使用屏蔽方式在放置栅格之前单独移除位置材料而形成

    公开(公告)号:US20120261765A1

    公开(公告)日:2012-10-18

    申请号:US13533807

    申请日:2012-06-26

    IPC分类号: H01L21/28 H01L27/092

    摘要: In a replacement gate approach in sophisticated semiconductor devices, the placeholder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.

    摘要翻译: 在复杂半导体器件中的替代栅极方法中,分别去除不同类型的栅电极结构的占位符材料。 此外,可以在所得到的栅极开口中选择性地形成电极金属,从而在调整不同类型的栅电极结构的各自的功函数方面提供优异的工艺条件。 在一个说明性实施例中,在不同类型的栅极电极结构中单独形成栅极开口可以基于设置在栅极层叠层中的掩模材料。

    Trench isolation structure having different stress
    27.
    发明授权
    Trench isolation structure having different stress 有权
    具有不同应力的沟槽隔离结构

    公开(公告)号:US08158486B2

    公开(公告)日:2012-04-17

    申请号:US11537809

    申请日:2006-10-02

    IPC分类号: H01L21/76

    摘要: By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of an appropriate mask layer, which may provide a patterned optical response for a lamp-based or laser-based anneal process. Consequently, the intrinsic stress of isolation trenches may be specifically adapted to the requirements of circuit elements, such as N-channel transistors and P-channel transistors.

    摘要翻译: 通过局部加热具有不同退火条件的隔离沟槽,可以在不同的隔离沟槽中获得不同大小的固有应力。 在一些说明性实施例中,可以基于合适的掩模层来实现不同的退火温度,其可以为基于灯或基于激光的退火工艺提供图案化的光学响应。 因此,隔离沟槽的固有应力可以特别适用于诸如N沟道晶体管和P沟道晶体管的电路元件的要求。