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公开(公告)号：US09337059B2
公开(公告)日：2016-05-10
申请号：US13215909
申请日：2011-08-23
Applicant: Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
Inventor： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC: H01L21/00 , H01L21/324 , H01L21/268 , H01L21/20 , H01L21/36 , H01L21/44
CPC classification number: H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
Abstract translation: 一种方法包括在晶片上进行退火。 晶片包括晶片边缘区域和由晶片边缘区域包围的内部区域。 在退火期间，施加在晶片边缘区域的一部分上的第一功率至少低于用于退火内部区域的第二功率。
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公开(公告)号：US08058134B2
公开(公告)日：2011-11-15
申请号：US12618052
申请日：2009-11-13
Applicant: Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
Inventor： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
IPC: H01L21/336
CPC classification number: H01L21/324 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833
Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
Abstract translation: 退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。 第二个持续时间比第一个持续时间长。 退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。
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公开(公告)号：US20100210086A1
公开(公告)日：2010-08-19
申请号：US12618052
申请日：2009-11-13
Applicant: Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
Inventor： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
IPC: H01L21/336
CPC classification number: H01L21/324 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833
Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
Abstract translation: 退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。 第二个持续时间比第一个持续时间长。 退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。
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公开(公告)号：US07736968B2
公开(公告)日：2010-06-15
申请号：US12259028
申请日：2008-10-27
Applicant: Keh-Chiang Ku , Cheng-Lung Hung , Li-Ting Wang , Chien-Hao Chen , Chien-Hao Huang , Wenli Lin , Yu-Chang Lin
Inventor： Keh-Chiang Ku , Cheng-Lung Hung , Li-Ting Wang , Chien-Hao Chen , Chien-Hao Huang , Wenli Lin , Yu-Chang Lin
IPC: H01L21/8238
CPC classification number: H01L21/28052 , H01L21/26506 , H01L21/26586 , H01L21/28506 , H01L29/1083 , H01L29/665 , H01L29/6659 , H01L29/7833
Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.
Abstract translation: 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极层; 将碳和氮掺杂到栅电极层中; 并且在掺杂碳和氮的步骤之后，分别构图栅极电介质层和栅极电极层以形成栅极电介质和栅电极。
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公开(公告)号：US07672101B2
公开(公告)日：2010-03-02
申请号：US11852799
申请日：2007-09-10
Applicant: Shu-Huei Lin , Chong-Gim Gan , Yi-Hsun Wu , Yu-Chang Lin
Inventor： Shu-Huei Lin , Chong-Gim Gan , Yi-Hsun Wu , Yu-Chang Lin
IPC: H02H9/00
CPC classification number: H01L27/0266
Abstract: A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven devise operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail VSS. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to Vss. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.
Abstract translation: 系统包括以第一电源电压Vdd1操作并具有CMOS输出的驱动装置。 驱动装置在低于第一电源电压Vdd1的第二电源电压Vdd2下工作，并具有带NMOS下拉晶体管的CMOS输入。 保护电路包括耦合到驱动装置的CMOS输出的第一电阻器和NMOS下拉晶体管的栅极。 寄生NPN双极结晶体管具有连接到NMOS下拉晶体管的栅极的漏极和耦合到较低电压电源轨VSS的源极。 第二个电阻将寄生NPN双极结晶体管的栅极连接到Vss。 第二电阻器的电阻大小用于控制寄生NPN双极结晶体管的触发电压，用于保护NMOS下拉晶体管的栅氧化层免受静电放电。
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Patent Agency Ranking
公开(公告)号：US06943103B2
公开(公告)日：2005-09-13
申请号：US10768848
申请日：2004-01-29
Applicant: Yia-Liang Kuo , Yu-Chang Lin , Yu-Ting Lin
Inventor： Yia-Liang Kuo , Yu-Chang Lin , Yu-Ting Lin
IPC: H01L21/44 , H01L21/60 , H01L23/485
CPC classification number: H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/05001 , H01L2224/05022 , H01L2224/05085 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2224/29099 , H01L2924/00 , H01L2224/05099
Abstract: Novel methods for reducing shear stress applied to solder bumps on a flip chip. The methods are particularly applicable to reducing temperature-induced shear stress on solder bumps located adjacent to an empty space on a flip chip during high-temperature testing of the chip. According to a first embodiment, the method includes providing an anchoring solder bump in each empty space on the flip chip. The anchoring solder bumps impart additional structural integrity to the flip chip and prevent shear-induced detachment of solder bumps from the flip chip, particularly those solder bumps located adjacent to each anchoring solder bump. According to a second embodiment, the method includes providing an anchoring solder bump in the empty space and then connecting the anchoring solder bump to an adjacent solder bump on the chip using a solder bridge.
Abstract translation: 用于减少施加到倒装芯片上的焊料凸块的剪切应力的新方法。 该方法特别适用于在芯片的高温测试期间减少与倒装芯片上的空白空间相邻的焊料凸块上的温度诱导剪切应力。 根据第一实施例，该方法包括在倒装芯片上的每个空白空间中提供锚定焊料凸块。 锚定焊料凸块对倒装芯片赋予额外的结构完整性，并防止焊料凸块从倒装芯片，特别是位于每个锚定焊料凸块附近的焊料凸块的剪切引起的分离。 根据第二实施例，该方法包括在空间中提供锚定焊料凸块，然后使用焊接桥将锚定焊料凸块连接到芯片上的相邻焊料凸块。
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公开(公告)号：US5877638A
公开(公告)日：1999-03-02
申请号：US718117
申请日：1996-09-18
Applicant: Yu-Chang Lin
Inventor： Yu-Chang Lin
IPC: H03K19/003 , H03K17/04
CPC classification number: H03K19/00361
Abstract: An output buffer with pull-up and push-down circuits. The pull-up circuits includes an initial voltage circuit providing an initial voltage to the pull-up terminal of the pull-up driver driving the output of the output buffer. The pull-up circuit also includes a circuit loop insuring that the ability of the pull-up circuit to drive the output terminal to the source voltage does not diminish in the latter half of the pull-up circuit's operation. The push-down circuit also insures that the drive capability of the push-down circuit does not diminish over the latter half of the push-down circuit's operation.
Abstract translation: 具有上拉和下拉电路的输出缓冲器。 上拉电路包括一个初始电压电路，为驱动输出缓冲器的输出的上拉驱动器的上拉端提供初始电压。 上拉电路还包括电路回路，确保上拉电路将输出端驱动到源极电压的能力在上拉电路的后半部分的操作中不会降低。 下拉电路还确保下推电路的驱动能力在下拉电路的操作的后半段不会降低。
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公开(公告)号：US10736471B2
公开(公告)日：2020-08-11
申请号：US16145219
申请日：2018-09-28
Applicant: Hsiang-Hung Wang , Yu-Chang Lin
Inventor： Hsiang-Hung Wang , Yu-Chang Lin
Abstract: A foam soap-providing machine with function of recycling soap-liquid, which comprises: a container containing a soap-liquid and having a soap-releasing portion; a shell-group including at least two detachable shell-bodies combinedly disposed on the outer peripheral surface of the soap-releasing portion; and a faucet mounted on the upper end of the soap-releasing portion and having a soap-feeding portion provided for flowing out the pressurized soap-liquid; wherein the soap-feeding portion has a joint end; wherein a foam-generating module used to generate a foam and a foam-recycling module used to recycle the extruded unused foam are comprised in the shell-group; thereby it can generate foam and recycle the remaining foam in the soap-releasing portion through a single motor. Accordingly, the present invention greatly saves the structural volume and prevents the soap-liquid from being dropped outside and wasted.
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公开(公告)号：US20200100628A1
公开(公告)日：2020-04-02
申请号：US16145219
申请日：2018-09-28
Applicant: Hsiang-Hung Wang , Yu-Chang Lin
Inventor： Hsiang-Hung Wang , Yu-Chang Lin
Abstract: A foam soap-providing machine with function of recycling soap-liquid, which comprises: a container containing a soap-liquid and having a soap-releasing portion; a shell-group including at least two detachable shell-bodies combinedly disposed on the outer peripheral surface of the soap-releasing portion; and a faucet mounted on the upper end of the soap-releasing portion and having a soap-feeding portion provided for flowing out the pressurized soap-liquid; wherein the soap-feeding portion has a joint end; wherein a foam-generating module used to generate a foam and a foam-recycling module used to recycle the extruded unused foam are comprised in the shell-group; thereby it can generate foam and recycle the remaining foam in the soap-releasing portion through a single motor. Accordingly, the present invention greatly saves the structural volume and prevents the soap-liquid from being dropped outside and wasted.
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公开(公告)号：US20130052837A1
公开(公告)日：2013-02-28
申请号：US13215909
申请日：2011-08-23
Applicant: Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
Inventor： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC: H01L21/268 , B23K26/00
CPC classification number: H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
Abstract translation: 一种方法包括在晶片上进行退火。 晶片包括晶片边缘区域和由晶片边缘区域包围的内部区域。 在退火期间，施加在晶片边缘区域的一部分上的第一功率至少低于用于退火内部区域的第二功率。
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