公开(公告)号：US20110256720A1

公开(公告)日：2011-10-20

申请号：US13169248

申请日：2011-06-27

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/28

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US07113006B2

公开(公告)日：2006-09-26

申请号：US11065840

申请日：2005-02-25

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman

IPC分类号： H03K5/22 ,  H03K5/153 ,  H01G23/00

CPC分类号： H02M3/07

摘要： A capacitor circuit having improved reliability includes at least first and second capacitors, a first terminal of the first capacitor connecting to a first source providing a first voltage, a first terminal of the second capacitor connecting to a second source providing a second voltage, the first voltage being greater than the second voltage. The capacitor further includes a voltage comparator having a first input for receiving a voltage representative of the first voltage, a second input for receiving a third voltage provided by a third source, and an output for generating a control signal. The control signal is a function of a difference between the voltage representative of the first voltage and the third voltage. A switch is connected to second terminals of the first and second capacitors. The switch is selectively operable in one of at least a first mode and a second mode in response to the control signal, wherein in the first mode the switch is operative to connect the first and second capacitors together in parallel, and in the second mode the switch is operative to connect the first and second capacitors together in series. The first mode is indicative of the voltage representative of the first voltage being less than or about equal to the third voltage, and the second mode is indicative of the voltage representative of the first voltage being greater than the third voltage.

摘要翻译： 具有改进的可靠性的电容器电路包括至少第一和第二电容器，第一电容器的第一端子连接到提供第一电压的第一源极，第二电容器的第一端子连接到提供第二电压的第二源极，第一电容器 电压大于第二电压。 电容器还包括电压比较器，具有用于接收表示第一电压的电压的第一输入端，用于接收由第三源极提供的第三电压的第二输入端和用于产生控制信号的输出端。 控制信号是代表第一电压和第三电压的电压之差的函数。 开关连接到第一和第二电容器的第二端子。 响应于控制信号，开关选择性地可操作于至少第一模式和第二模式之一中，其中在第一模式中，开关可操作以并联连接第一和第二电容器，并且在第二模式中， 开关可操作以串联连接第一和第二电容器。 第一模式表示代表第一电压的电压小于或等于第三电压，第二模式表示代表第一电压的电压大于第三电压。

公开(公告)号：US07093171B2

公开(公告)日：2006-08-15

申请号：US10115348

申请日：2002-04-03

申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

公开(公告)号：US06992917B2

公开(公告)日：2006-01-31

申请号：US10736414

申请日：2003-12-15

申请人： William R. Dachtera ,  Louis L. Hsu ,  Rajiv V. Joshi

发明人： William R. Dachtera ,  Louis L. Hsu ,  Rajiv V. Joshi

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： H03K19/00384 ,  H01L27/1203 ,  H01L29/78612

摘要： An integrated circuit (IC), random access memory on an IC and method of neutralizing device floating body effects. A floating body effect monitor monitors circuit/array activity and selectively provides an indication of floating body effect manifestation from inactivity, including the lapse of time since the most recent activity or memory access. A pulse generator generates a neutralization pulse in response to an indication of inactivity. A neutralization pulse distribution circuit passes the neutralization pulse to blocks in the circuit path or to array cells.

摘要翻译： 集成电路（IC），IC上的随机存取存储器以及中和器件浮体效应的方法。 浮体效应监视器监视电路/阵列活动，并且选择性地提供来自不活动的浮体影响表现的指示，包括自最近的活动或存储器访问以来的时间流逝。 脉冲发生器响应于不活动的指示产生中和脉冲。 中和脉冲分配电路将中和脉冲传递到电路路径中的块或阵列单元。

公开(公告)号：US06906354B2

公开(公告)日：2005-06-14

申请号：US09880223

申请日：2001-06-13

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

IPC分类号： G11C11/39 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/12 ,  H01L29/32 ,  H01L29/423

CPC分类号： G11C11/39 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1112 ,  H01L27/1203

摘要： A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath the horizontally stacked pseudo-TFT transfer gate. A method is also presented for fabricating the T-RAM array having the buried vertical thyristors, the horizontally stacked pseudo-TFT transfer gates and the planar cell structure.

摘要翻译： 呈现具有多个T-RAM单元的T-RAM阵列，其中每个T-RAM单元具有双器件。 每个T-RAM单元是平面的并且具有埋入的垂直晶闸管和水平堆叠的伪TFT传输门。 埋置的垂直晶闸管位于水平堆叠的伪TFT传输门的下方。 还提出了一种用于制造具有埋入垂直晶闸管，水平堆叠的伪TFT传输门和平面单元结构的T-RAM阵列的方法。

公开(公告)号：US06876250B2

公开(公告)日：2005-04-05

申请号：US10345039

申请日：2003-01-15

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton

IPC分类号： G01K7/01 ,  G05F3/30 ,  H01L23/34 ,  G05F1/10

CPC分类号： G05F3/30 ,  G01K7/015 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one μW. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit. The low-power circuits of the sensor circuit extend battery lifetime and data retention time of the cells of the at least one memory unit.

摘要翻译： 提供了组合的低压，低功率带隙参考和温度传感器电路，用于提供带隙参考参数，并且用于使用频带参考参数来感测诸如eDRAM存储器单元或CPU芯片的芯片的温度， 间隙参考参数。 组合的传感器电路对电源电压和芯片温度的变化不敏感。 包含组合传感器电路的两个电路（即带隙基准和温度传感器电路）的功耗小于1μW。 组合传感器电路可用于监测局部或全局芯片温度。 结果可用于（1）调节DRAM阵列刷新周期时间，例如温度越高，刷新周期时间越短，（2）启动片上或片外冷却或加热装置来调节 芯片温度，（3）调节内部产生的电压电平，（4）调整CPU（或微处理器）的时钟频率，即频率，使芯片不会过热。 本发明的组合带隙参考和温度传感器电路可以在具有至少一个存储器单元的电池供电的装置内实现。 传感器电路的低功率电路延长了至少一个存储器单元的单元的电池寿命和数据保持时间。

公开(公告)号：US06631503B2

公开(公告)日：2003-10-07

申请号：US09755860

申请日：2001-01-05

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  John A. Fifield

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  John A. Fifield

IPC分类号： G06F1750

CPC分类号： G06F1/206 ,  H03K2005/00143 ,  Y02D10/16

摘要： The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a binary output which is received by a programmable table circuit of the timing delay system. The programmable table circuit outputs a binary output corresponding to the received binary output. The timing delay system further includes a temperature dependent timing delay circuit having inputs for receiving the binary output of the programmable table circuit and an output for outputting a timing delay signal for delaying a clock by a timing delay corresponding to the binary output of the programmable table circuit. The band-gap reference can be a temperature independent band-gap reference voltage having a constant-voltage value or a temperature dependent band-gap reference current having a constant-current value. A method is also provided for varying a characteristic of a timing delay signal in accordance with variations of the on-chip temperature of an integrated circuit chip. The method includes the steps of generating a reference parameter; sensing the on-chip temperature of the integrated circuit chip by utilizing at least the reference parameter; providing the sensed on-chip temperature as a binary reading; using the binary reading for providing a respective binary code indicating a timing delay; and varying the characteristic of the timing delay signal, such as the signal's rise time, in accordance with the binary code.

公开(公告)号：US06574127B2

公开(公告)日：2003-06-03

申请号：US09820592

申请日：2001-03-29

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David R. Hanson

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David R. Hanson

IPC分类号： G11C506

CPC分类号： G11C5/063

摘要： A dataline wiring structural system is provided for an eDRAM which suppresses coupling and switching noise associated with datalines by providing a plurality of metal levels upon which the datalines are positioned. Each of the datalines carrying a differential signal includes at least one vertical twist in which the true and complementary signal components of the differential signal change position from the one metal level of the plurality of metal levels to another level.

摘要翻译： 为eDRAM提供数据线接线结构系统，其通过提供数据线定位在其上的多个金属电平来抑制与数据线相关联的耦合和开关噪声。 携带差分信号的每个数据线包括至少一个垂直扭转，其中差分信号的真实和互补信号分量从多个金属电平的一个金属电平改变到另一个电平。

公开(公告)号：US06552398B2

公开(公告)日：2003-04-22

申请号：US09760970

申请日：2001-01-16

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

IPC分类号： H01L2978

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/1027 ,  H01L27/1203

摘要： A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.

摘要翻译： 提出了一种具有平面单元结构的T-RAM阵列，其包括多个T-RAM单元。 通过使用掺杂多晶硅来形成多个T-RAM单元中的每一个以形成自对准扩散区域以产生低接触电阻p +扩散区域。 硅化p +多晶硅导线优选地用于将多个T-RAM单元中的每一个连接到参考电压Vref。 通过将n +注入植入到每两个字线之间的间隙中，在每两个字线之间形成自对准结区。 自对准结区域为现有技术的T-RAM单元提供从8F2的单元大小到小于或等于6F2的单元大小的T-RAM单元尺寸的减小。 优选地，T-RAM阵列构建在半导体硅绝缘体（SOI）晶片上，以减少结电容并提高可扩展性。

公开(公告)号：US06492662B2

公开(公告)日：2002-12-10

申请号：US09835732

申请日：2001-04-16

申请人： Louis L. Hsu ,  Rajiv V. Joshi

发明人： Louis L. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L2972

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual vertical devices. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure.

摘要翻译： 呈现具有多个T-RAM单元的T-RAM阵列，其中每个T-RAM单元具有双垂直设备。 每个T-RAM单元具有垂直晶闸管和垂直传输门。 每个晶闸管的顶表面与T-RAM阵列内的每个传输栅极的顶表面共面以提供用于T-RAM阵列的平面单元结构。 还提出了一种用于制造具有垂直晶闸管，垂直传输门和平面单元结构的T-RAM阵列的方法。