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    Techniques for impeding reverse engineering
    1.
    发明授权
    Techniques for impeding reverse engineering 有权
    阻止逆向工程的技术

    公开(公告)号：US07994042B2

    公开(公告)日：2011-08-09

    申请号：US11924735

    申请日：2007-10-26

    申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

    发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

    摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

    Flexible row redundancy system
    2.
    发明授权
    Flexible row redundancy system 失效
    灵活的行冗余系统

    公开(公告)号：US07774660B2

    公开(公告)日：2010-08-10

    申请号：US12131307

    申请日：2008-06-02

    申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

    发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

    IPC分类号： G11C29/00

    CPC分类号： G11C29/808

    摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

    摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

    Suppression of leakage currents in VLSI logic and memory circuits
    3.
    发明授权
    Suppression of leakage currents in VLSI logic and memory circuits 有权
    VLSI逻辑和存储器电路中泄漏电流的抑制

    公开(公告)号：US06683805B2

    公开(公告)日：2004-01-27

    申请号：US10067411

    申请日：2002-02-05

    申请人： Rajiv V. Joshi ,  Louis L. Hsu ,  Azeez J. Bhavnagarwala

    发明人： Rajiv V. Joshi ,  Louis L. Hsu ,  Azeez J. Bhavnagarwala

    IPC分类号： G11C11413

    CPC分类号： G11C11/412

    摘要： An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. A method is also provided for providing a power supply voltage to at least one circuit of a system.

    摘要翻译： 提供一种SRAM系统，其具有包括至少一个接收第一电源电压的电池的SRAM单元阵列和用于向至少一个电路的至少一个选定电路提供第二电源电压的功率控制电路。 该系统是存储器阵列和逻辑系统之一，并且至少一个电路的电路是存储器阵列的存储单元，存储器阵列的读出放大器和逻辑系统的路径之一。 还提供了一种用于向系统的至少一个电路提供电源电压的方法。

    Refractory metal capped low resistivity metal conductor lines and vias
    6.
    发明授权
    Refractory metal capped low resistivity metal conductor lines and vias 失效
    耐火金属封盖的低电阻金属导线和通孔

    公开(公告)号：US5300813A

    公开(公告)日：1994-04-05

    申请号：US841967

    申请日：1992-02-26

    申请人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

    发明人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

    IPC分类号： H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/440 ,  H01L29/460

    CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959

    摘要： A contact structure for a semiconductor device having a first refractory metal layer formed only at the bottom of a contact hole. The first refractory metal is selected from a group comprising titanium (Ti), titanium alloys or compounds such as Ti/TiN, tungsten (W), titanium/tungsten (Ti/W) alloys, or chromium (Cr) or tantalum (Ta) and their alloys or some other suitable material. A low resistivity layer comprising a single, binary or ternary metalization is deposited over the first refractory metal layer in the contact hole by a method such as PVD using evaporation or collimated sputtering. The low resistivity layer has side walls which taper inwardly toward one another with increasing height of the layer and the low resistivity layer does not contact the side walls of the contact hole. The low resistivity layer may be Al.sub.x Cu.sub.y (x+y=1; x.gtoreq.0, y.gtoreq.0), ternary alloys such as Al-Pd-Cu or multicomponent alloys such as Al-Pd-Nb-Au. A second refractory metal layer is deposited over the low resistivity layer. The second refractory metal layer may be tungsten, cobalt, nickel, molybdenum or alloys/compounds such as Ti/TiN. The first and second refractory metal layers completely encapsulate the low resistivity layer. The first and second refractory metal layers can comprise an alloy containing silicon with a higher incorporated silicon content near the top of the contact hold present as a distinct or graded composition than at a location closer to the bottom of the contact hole.

    摘要翻译： 一种用于半导体器件的接触结构，其具有仅在接触孔的底部形成的第一难熔金属层。 第一难熔金属选自钛（Ti），钛合金或Ti / TiN，钨（W），钛/钨（Ti / W）合金或铬（Cr）或钽（Ta） 及其合金或其他合适的材料。 包含单一二元或三元金属化的低电阻率层通过诸如使用蒸发或准直溅射的PVD的方法沉积在接触孔中的第一难熔金属层上。 低电阻率层具有随着层的高度逐渐向内逐渐向内逐渐变细的侧壁，低电阻层不接触接触孔的侧壁。 低电阻率层可以是AlxCuy（x + y = 1; x> = 0，y> = 0），诸如Al-Pd-Cu的三元合金或诸如Al-Pd-Nb-Au的多组分合金。 在低电阻率层上沉积第二难熔金属层。 第二耐火金属层可以是钨，钴，镍，钼或诸如Ti / TiN的合金/化合物。 第一和第二难熔金属层完全封装低电阻率层。 第一和第二难熔金属层可以包含含有硅的合金，其中接合保持层的顶部附近具有更高的掺入硅含量，作为不同或分级的组成，而不是靠近接触孔底部的位置。

    Techniques for impeding reverse engineering
    7.
    发明授权
    Techniques for impeding reverse engineering 有权
    阻止逆向工程的技术

    公开(公告)号：US08324102B2

    公开(公告)日：2012-12-04

    申请号：US13169248

    申请日：2011-06-27

    申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

    发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

    摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

    Metal-insulator-metal capacitor and method of fabricating same
    9.
    发明授权
    Metal-insulator-metal capacitor and method of fabricating same 失效
    金属绝缘体金属电容器及其制造方法

    公开(公告)号：US06964908B2

    公开(公告)日：2005-11-15

    申请号：US10643307

    申请日：2003-08-19

    申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Chun-Yung Sung

    发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Chun-Yung Sung

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L21/308

    CPC分类号： H01G4/228 ,  H01G4/33 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

    摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insulating layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.

    摘要翻译： 一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层 沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。 一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少形成第一开口和至少第一绝缘层中的第二开口，在第二开口上沉积掩模 在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。 描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

    Method to improve cache capacity of SOI and bulk
    10.
    发明授权
    Method to improve cache capacity of SOI and bulk 有权
    提高SOI和散货的高速缓存容量的方法

    公开(公告)号：US06934182B2

    公开(公告)日：2005-08-23

    申请号：US10678508

    申请日：2003-10-03

    申请人： Yuen H. Chan ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Robert Chi-Foon Wong

    发明人： Yuen H. Chan ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Robert Chi-Foon Wong

    IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： G11C11/412

    摘要： Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

    摘要翻译： 提供了设计具有更大稳定性和/或更小单元尺寸的6T SRAM单元的方法。 6T SRAM单元具有一对存取晶体管（NFET），一对上拉晶体管（PFET）和一对下拉晶体管（NFET），其中存取晶体管具有比下拉电阻高的阈值电压 晶体管，这使得SRAM单元能够在单元访问期间有效地保持逻辑“0”，从而增加了单元的稳定性，特别是对于“半选择”期间的单元。 此外，可以减小下拉晶体管的沟道宽度，从而降低高性能六晶体管SRAM单元的尺寸，而不影响单元在访问期间的稳定性。 并且，通过减小单元尺寸，芯片的整体设计布局也可能降低。