公开(公告)号：US20200242273A1

公开(公告)日：2020-07-30

申请号：US16726284

申请日：2019-12-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long CHANG ,  Chia-Jung CHEN ,  Chin-Hung CHANG ,  Ken-Hui CHEN

IPC: G06F21/72 ,  G06F12/1009 ,  G06F21/62

Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

公开(公告)号：US20200186339A1

公开(公告)日：2020-06-11

申请号：US16793986

申请日：2020-02-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung HUNG ,  Kuen-Long CHANG ,  Ken-Hui CHEN ,  Shih-Chang HUANG ,  Chin-Hung CHANG ,  Chen-Chia FAN

IPC: H04L9/08 ,  H04L9/32 ,  G06F21/62 ,  G06F3/06 ,  G06F12/0877

Abstract: A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.

公开(公告)号：US20200036539A1

公开(公告)日：2020-01-30

申请号：US16592850

申请日：2019-10-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung HUNG ,  Kuen-Long CHANG ,  Ken-Hui CHEN ,  Shih-Chang HUANG

IPC: H04L9/32 ,  G06F3/06 ,  G09C1/00 ,  G11C16/22 ,  H04L9/08 ,  H04L9/14 ,  G06F7/58 ,  G06F11/10 ,  G06F12/02 ,  G06F12/14 ,  G06F21/31 ,  G06F21/60 ,  G06F21/75 ,  G11C7/24 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26 ,  G11C8/20 ,  G06F13/42 ,  G11C11/16

Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

公开(公告)号：US20160204695A1

公开(公告)日：2016-07-14

申请号：US14737788

申请日：2015-06-12

Applicant: Macronix International Co., Ltd.

Inventor： Wu-Chin PENG ,  Hsing-Yu LIU ,  Chun-Yi LEE ,  Ken-Hui CHEN ,  Kuen-Long CHANG ,  Chun Hsiung HUNG

IPC: H02M3/07

CPC classification number: H02M3/07 ,  H02M3/073 ,  H02M2003/075 ,  H02M2003/077

Abstract: A charge pump circuit includes a plurality of branches coupled in parallel, each branch including a plurality of sub-blocks coupled in series, and each sub-block including a unit pump circuit. The charge pump circuit also includes a plurality of clock transfer circuits coupled to corresponding ones of the plurality of branches for providing clock signals to the corresponding branches. The sub-blocks of different branches are enabled and driven by the clock signals at different times.

Abstract translation: 电荷泵电路包括并联耦合的多个分支，每个分支包括串联耦合的多个子块，每个子块包括单元泵电路。 电荷泵电路还包括耦合到多个分支中的相应分支的多个时钟传送电路，用于向对应的分支提供时钟信号。 不同分支的子块由不同时间的时钟信号使能和驱动。

公开(公告)号：US20150340071A1

公开(公告)日：2015-11-26

申请号：US14719678

申请日：2015-05-22

Applicant: Macronix International Co., Ltd.

Inventor： Ken-Hui CHEN ,  Kuen Long CHANG ,  Chin-Hung CHANG

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/222

Abstract: A memory device includes a variable strobe interface configured to select one of a data queue strobe signal or a system clock signal to signal initiation of data receipt at the memory device.

Abstract translation: 存储器件包括可变选通接口，该可变选通接口被配置为选择数据队列选通信号或系统时钟信号中的一个，以在存储器设备处发信号通知数据接收。

公开(公告)号：US20150286405A1

公开(公告)日：2015-10-08

申请号：US14677321

申请日：2015-04-02

Applicant: Macronix International Co., Ltd.

Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Chang-Ting CHEN

IPC: G06F3/06

CPC classification number: G06F9/00 ,  G06F1/12 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C16/00 ,  G11C29/023

Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.

Abstract translation: 非易失性存储器件包括存储器芯，其存储要根据外部时钟信号从存储器核心输出的数据，输入缓冲器接收外部时钟信号并提供输入时钟信号;以及同步电路，包括延迟电路和 配置为接收输入时钟信号，提供输出时钟信号，并将输出时钟信号与外部时钟信号同步。 该装置还包括接收输出时钟信号的数据选通输出缓冲器，并提供具有相对于外部时钟信号可配置的信号延迟的数据选通信号，接收数据和输出时钟信号的时钟控制电路元件并同步地输出数据 以及延迟控制电路，其向延迟电路提供延迟控制信号，以修改数据选通信号的信号延迟。