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公开(公告)号：US20200175363A1
公开(公告)日：2020-06-04
申请号：US16450334
申请日：2019-06-24
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
Abstract: A method for accelerating a convolution of a kernel matrix over an input matrix for computation of an output matrix using in-memory computation involves storing in different sets of cells, in an array of cells, respective combinations of elements of the kernel matrix or of multiple kernel matrices. To perform the convolution, a sequence of input vectors from an input matrix is applied to the array. Each of the input vectors is applied to the different sets of cells in parallel for computation during the same time interval. The outputs from each of the different sets of cells generated in response to each input vector are sensed to produce a set of data representing the contributions of that input vector to multiple elements of an output matrix. The sets of data generated across the input matrix are used to produce the output matrix.
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公开(公告)号：US20190221263A1
公开(公告)日：2019-07-18
申请号：US16233404
申请日：2018-12-27
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min LEE , Yu-Yu LIN
IPC: G11C16/04 , G11C16/08 , H01L29/792 , H01L29/788 , G11C16/26 , G11C16/10 , G06N3/063 , G06F7/544
CPC classification number: G11C16/0483 , G06F7/5443 , G06N3/0635 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/7881 , H01L29/792
Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.
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公开(公告)号：US20250111874A1
公开(公告)日：2025-04-03
申请号：US18476411
申请日：2023-09-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan LIN , Feng-Min LEE , Ming-Hsiu LEE , Yu-Yu LIN
IPC: G11C11/4096 , G11C11/4074 , G11C11/408 , G11C11/4091
Abstract: A reservoir device, comprises a first transistor and a second transistor. A gate of the first transistor is coupled to a write word line, a drain of the first transistor is coupled to a write bit line. A source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to a source of the first transistor. A storage node is located on a coupling point between the gate of the second transistor and the source of the first transistor. The reservoir device selectively performs a write operation, a read operation or a refresh operation in response to an input voltage received by the write word line, the write bit line, the read source line and the read bit line respectively.
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公开(公告)号：US20240244849A1
公开(公告)日：2024-07-18
申请号：US18153376
申请日：2023-01-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
CPC classification number: H10B63/80 , H10N70/011 , H10N70/24 , H10N70/826
Abstract: A semiconductor device includes a resistor. The resistor includes two bottom electrodes adjacent to each other, a resistive layer, a top electrode and a conductive sidewall. The resistive layer is disposed on the two bottom electrodes. The top electrode is disposed on the resistive layer. The conductive sidewall surrounds the top electrode and is electrically connected to the top electrode and a bottom electrode of the two bottom electrodes. The top electrode overlaps the two bottom electrodes in the first direction, and extends above the two bottom electrodes along a second direction different from the first direction.
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Patent Agency Ranking
公开(公告)号：US20240242757A1
公开(公告)日：2024-07-18
申请号：US18297055
申请日：2023-04-07
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min LEE , Po-Hao TSENG , Yu-Yu LIN , Ming-Hsiu LEE
IPC: G11C11/4096 , G11C11/405
CPC classification number: G11C11/4096 , G11C11/405
Abstract: A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.
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26.发明公开公开(公告)号：US20230420043A1
公开(公告)日：2023-12-28
申请号：US17848521
申请日：2022-06-24
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
CPC classification number: G11C13/004 , G11C13/0069 , G11C13/0009 , G06F7/5443
Abstract: A memory device and an operation method thereof for performing a multiply-accumulate operation are provided. The memory device includes at least one memory string, a plurality of data lines and a string line. The memory string includes a plurality of unit cells having a plurality of stored values. The data lines are respectively connected to the unit cells to receive a plurality of data signals having a plurality of inputting values. When the data signals are inputted into the unit cells, a plurality of nodes among the unit cells are kept at identical voltages. The string line is connected to the memory string to receive a sensing signal and obtain a measured value representing a sum-of-product result of the inputting values and the stored values. The data signals and the sensing signal are received at different time.
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公开(公告)号：US20200034684A1
公开(公告)日：2020-01-30
申请号：US16222222
申请日：2018-12-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
IPC: G06N3/02 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/11524 , H01L29/788
Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programming/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.
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28.发明申请公开(公告)号：US20190286419A1
公开(公告)日：2019-09-19
申请号：US15922359
申请日：2018-03-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
Abstract: A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each including a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable resistors in the array with resistances corresponding to values of a weight factor Wmn for the corresponding cell. Alternatively, the resistances can be programmed during manufacture. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.
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公开(公告)号：US20160218286A1
公开(公告)日：2016-07-28
申请号：US14750801
申请日：2015-06-25
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
CPC classification number: H01L45/146 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1633
Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.
Abstract translation: 本文描述了基于金属氧化物的存储器件及其制造方法。 一种用于制造存储单元的方法包括在绝缘层中形成的通孔中形成底部粘附层。 在底部粘合层中形成底部导电塞。 在底部粘合层和底部导电插塞上形成顶部粘附层。 在顶部粘合层中形成顶部导电塞。 其中底部和顶部粘附层的厚度可以彼此不同。
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