公开(公告)号：US12080644B2

公开(公告)日：2024-09-03

申请号：US17929638

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Qui V. Nguyen ,  Chang H. Siau

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/535 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.

公开(公告)号：US12007860B2

公开(公告)日：2024-06-11

申请号：US18075958

申请日：2022-12-06

Applicant: Micron Technology, Inc.

Inventor： Sri Rama Namala ,  Lu Tong ,  Kristopher Kopel ,  Sheng-Huang Lee ,  Chang H. Siau

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/26

CPC classification number: G06F11/2094 ,  G11C16/0483 ,  G06F2201/85 ,  G11C16/26

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

公开(公告)号：US20230111510A1

公开(公告)日：2023-04-13

申请号：US18075958

申请日：2022-12-06

Applicant: Micron Technology, Inc.

Inventor： Sri Rama Namala ,  Lu Tong ,  Kristopher Kopel ,  Sheng-Huang Lee ,  Chang H. Siau

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/26

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

公开(公告)号：US20230061258A1

公开(公告)日：2023-03-02

申请号：US17718217

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Raj K. Bansal ,  Takehiro Hasegawa ,  Chang H. Siau

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

公开(公告)号：US20230022858A1

公开(公告)日：2023-01-26

申请号：US17960252

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US20220189570A1

公开(公告)日：2022-06-16

申请号：US17247435

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US11354067B2

公开(公告)日：2022-06-07

申请号：US16947525

申请日：2020-08-05

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy C. Kavalipurapu ,  Chang H. Siau ,  Shigekazu Yamada

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/04

Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.