公开(公告)号：US20210391257A1

公开(公告)日：2021-12-16

申请号：US16900204

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Qui V. Nguyen ,  Chang H. Siau

IPC: H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/535

Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.

公开(公告)号：US20220068325A1

公开(公告)日：2022-03-03

申请号：US17034540

申请日：2020-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Michele Piccardi ,  Qui V. Nguyen

IPC: G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.

公开(公告)号：US12080644B2

公开(公告)日：2024-09-03

申请号：US17929638

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Qui V. Nguyen ,  Chang H. Siau

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/535 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.

公开(公告)号：US11437318B2

公开(公告)日：2022-09-06

申请号：US16900204

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Qui V. Nguyen ,  Chang H. Siau

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.

公开(公告)号：US11670346B2

公开(公告)日：2023-06-06

申请号：US17034540

申请日：2020-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Michele Piccardi ,  Qui V. Nguyen

IPC: G11C16/10 ,  G11C7/10 ,  G11C7/22 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C7/1018 ,  G11C7/1096 ,  G11C7/222 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

Abstract: Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.

公开(公告)号：US20220415794A1

公开(公告)日：2022-12-29

申请号：US17929638

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Qui V. Nguyen ,  Chang H. Siau

IPC: H01L23/528 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11582 ,  H01L23/535

Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.