公开(公告)号：US11205480B1

公开(公告)日：2021-12-21

申请号：US17018786

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C13/00 ,  G11C11/16

Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.

公开(公告)号：US11205479B2

公开(公告)日：2021-12-21

申请号：US15931080

申请日：2020-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Fredric Schreck ,  Hari Giduturi

IPC: G11C13/00

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.

公开(公告)号：US20190341919A1

公开(公告)日：2019-11-07

申请号：US16517000

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hari Giduturi

IPC: H03K19/0185 ,  H03K5/003 ,  H03K17/10

Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.

公开(公告)号：US10153040B2

公开(公告)日：2018-12-11

申请号：US15828402

申请日：2017-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US12254948B2

公开(公告)日：2025-03-18

申请号：US17723798

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C5/06 ,  G11C5/14 ,  H01L25/065

Abstract: A memory device standby procedure can include idling a first memory device in a low-power standby mode, the first memory device coupled to a memory interface that couples multiple memory devices to a host and includes a command line (CA) and a standby exit line (EX), and the first memory device can include a primary die coupled to multiple secondary dies using an intra-package bus. At the first memory device, the procedure can include waking receiver circuitry on the primary die in response to a state change on the standby exit line, and sampling the command line using logic circuitry on the primary die. When a wakeup message on the command line comprises a chip identification that corresponds to the first memory device, the procedure can include initiating a standby exit procedure for the first memory device.

公开(公告)号：US12020743B2

公开(公告)日：2024-06-25

申请号：US18182305

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C13/00 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2211/4013

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US12014765B2

公开(公告)日：2024-06-18

申请号：US17723740

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C11/4076 ,  G11C5/06 ,  H01L25/065 ,  G11C5/04

CPC classification number: G11C11/4076 ,  G11C5/06 ,  H01L25/0657 ,  G11C5/04 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A packaged memory device can include a primary memory die coupled to a shared intra-package communication bus and coupled to an external host device using a host interface bus, and the host interface bus can include a host clock channel. The memory device can include multiple secondary dies coupled to the intra-package communication bus, and each of the secondary dies can be configured to receive the same messages from the primary memory die using the intra-package communication bus. The primary memory die can send a first message to, or receive a first message from, a particular one of the secondary dies using the intra-package communication bus, and the first message can include a first chip identification field that exclusively indicates the particular one of the secondary dies.

公开(公告)号：US20230335192A1

公开(公告)日：2023-10-19

申请号：US17723673

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jason M. Brown

IPC: G11C13/00 ,  H01L25/065 ,  G11C11/16

CPC classification number: G11C13/0061 ,  H01L25/0657 ,  G11C11/1693 ,  H01L2225/06506 ,  H01L2225/06541

Abstract: A memory device includes a substrate with two or more memory die stacked in a three-dimensional stacked (3DS) configuration. The memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The two or more memory die each include its own plurality of memory cells. Furthermore, each of the two or more memory die include a local control circuitry configured to receive or transmit a divided clock that is based on the clock.

公开(公告)号：US11763910B2

公开(公告)日：2023-09-19

申请号：US17506421

申请日：2021-10-20

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C29/12 ,  G11C29/42 ,  G11C7/10

CPC classification number: G11C29/42 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/12015

Abstract: Memory devices may perform read operations and write operations with different bit error correction rates to satisfy a bit error correction rate. However, improving the bit error correction rate of the memory device using a single type of read command and/or write commands may result in longer read and write commands. Moreover, using longer read and write commands may result in undesirable higher memory power consumption and may reduce memory throughput. Accordingly, memory operations are described that may use combination of commands with increased bit error correction capability and reduced bit error correction capability. For example, the read operations may use multiple (e.g., at least two) sets or groupings of read commands and the write operations may use multiple (e.g., at least two) sets or groupings of write commands.

公开(公告)号：US20230215489A1

公开(公告)日：2023-07-06

申请号：US18182305

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C13/00

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0002 ,  G11C13/0069 ,  G11C13/003 ,  G11C13/0023 ,  G11C2013/0045 ,  G11C2211/4013

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.