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    PROGRESSIVE LENGTH ERROR CONTROL CODE
    21.
    发明申请
    PROGRESSIVE LENGTH ERROR CONTROL CODE 有权

    公开(公告)号：US20210034461A1

    公开(公告)日：2021-02-04

    申请号：US17075424

    申请日：2020-10-20

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

    Dynamic power-down of a block of a pattern-recognition processor
    22.
    发明授权
    Dynamic power-down of a block of a pattern-recognition processor 有权

    公开(公告)号：US10152113B2

    公开(公告)日：2018-12-11

    申请号：US15206844

    申请日：2016-07-11

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06F1/32 ,  G06F7/02 ,  G06N5/04

    Abstract: A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block.

    Correcting recurring errors in memory
    25.
    发明授权
    Correcting recurring errors in memory 有权
    纠正内存中的重复错误

    公开(公告)号：US09411694B2

    公开(公告)日：2016-08-09

    申请号：US14178867

    申请日：2014-02-12

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06F11/00 ,  G06F11/16

    CPC classification number: G06F11/1658 ,  G06F11/1048 ,  G06F2201/82

    Abstract: The present disclosure includes apparatuses and methods for correcting recurring errors in memory. A number of embodiments include determining whether a first subset of a group of memory cells has a recurring error associated therewith using a second subset of the group of memory cells, and responsive to a determination that the first subset of the group of memory cells has a recurring error associated therewith, correcting the recurring error using the second subset of the group of memory cells.

    Abstract translation: 本公开包括用于校正存储器中的重复错误的装置和方法。 多个实施例包括确定一组存储器单元的第一子集是否具有与其相关联的循环错误，使用存储器单元组的第二子集，并且响应于确定该组存储器单元的第一子集具有 与之相关的重复出现的错误，使用该组存储器单元的第二子集来校正循环错误。

    CORRECTING RECURRING ERRORS IN MEMORY
    27.
    发明申请
    CORRECTING RECURRING ERRORS IN MEMORY 有权
    更正内存中的回复错误

    公开(公告)号：US20150227441A1

    公开(公告)日：2015-08-13

    申请号：US14178867

    申请日：2014-02-12

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06F11/16

    CPC classification number: G06F11/1658 ,  G06F11/1048 ,  G06F2201/82

    Abstract: The present disclosure includes apparatuses and methods for correcting recurring errors in memory. A number of embodiments include determining whether a first subset of a group of memory cells has a recurring error associated therewith using a second subset of the group of memory cells, and responsive to a determination that the first subset of the group of memory cells has a recurring error associated therewith, correcting the recurring error using the second subset of the group of memory cells.

    Abstract translation: 本公开包括用于校正存储器中的重复错误的装置和方法。 多个实施例包括确定一组存储器单元的第一子集是否具有与其相关联的循环错误，使用存储器单元组的第二子集，并且响应于确定该组存储器单元的第一子集具有 与之相关的重复出现的错误，使用该组存储器单元的第二子集来校正循环错误。

    APPARATUSES AND METHODS FOR ADAPTIVE CONTROL OF MEMORY
    28.
    发明申请
    APPARATUSES AND METHODS FOR ADAPTIVE CONTROL OF MEMORY 审中-公开
    记忆自适应控制的装置和方法

    公开(公告)号：US20140281149A1

    公开(公告)日：2014-09-18

    申请号：US13911797

    申请日：2013-06-06

    Applicant: Micron Technology, Inc.

    Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

    IPC: G06F12/08 ,  G06F12/02

    CPC classification number: G06F12/023 ,  G06F12/0292 ,  G06F13/1694 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

    Abstract translation: 公开了用于存储器自适应控制的装置和方法。 一个示例性装置包括被配置为运行操作系统的处理单元和耦合到处理单元的存储器。 所述存储器经配置以经由存储器总线与所述处理单元通信。 示例设备还可以包括自适应存储器控制器，其被配置为从存储器和处理单元接收监视的统计数据。 自适应存储器控制器被配置为基于所监视的统计数据来管理存储器。

    MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA
    29.
    发明申请
    MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA 有权
    使用ECC与标记位来识别修改的数据的存储器系统和方法

    公开(公告)号：US20130254626A1

    公开(公告)日：2013-09-26

    申请号：US13855534

    申请日：2013-04-02

    Applicant: MICRON TECHNOLOGY, INC

    Inventor： J. Thomas Pawlowski ,  John F. SCHRECK

    IPC: G06F11/10

    CPC classification number: H03M13/151 ,  G06F11/10 ,  G06F11/1044 ,  G11C7/1006 ,  G11C11/406 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062

    Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device, The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

    Abstract translation: DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据相对应的ECC校正子。DRAM装置还包括使ECC校正子存储在DRAM装置中的ECC控制器。 当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。 每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。 在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。 可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

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