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公开(公告)号：US11714443B2
公开(公告)日：2023-08-01
申请号：US17666124
申请日：2022-02-07
Applicant: Micron Technology, Inc.
Inventor： Anupriya Chakraborty , John David Porter , Alan John Wilson
Abstract: Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.
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公开(公告)号：US11483013B2
公开(公告)日：2022-10-25
申请号：US17307641
申请日：2021-05-04
Applicant: Micron Technology, Inc.
Inventor： John David Porter
Abstract: Error correction procedures for a memory device including a memory die having an array of memory cells including a plurality of banks are described. The memory die includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.
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公开(公告)号：US20220028433A1
公开(公告)日：2022-01-27
申请号：US16934213
申请日：2020-07-21
Applicant: Micron Technology, Inc.
Inventor： John David Porter , Suryanarayana B. Tatapudi
Abstract: Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.
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公开(公告)号：US11005501B2
公开(公告)日：2021-05-11
申请号：US16279483
申请日：2019-02-19
Applicant: Micron Technology, Inc.
Inventor： John David Porter
Abstract: Some instances of a memory device include a memory die having an array of memory cells including a plurality of banks. In some cases, the memory die further includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. In some examples, the memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.
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公开(公告)号：US20200266838A1
公开(公告)日：2020-08-20
申请号：US16279483
申请日：2019-02-19
Applicant: Micron Technology, Inc.
Inventor： John David Porter
Abstract: Methods, systems, and devices for error correction on a memory device are described. Examples may include a memory die having an array of memory cells including a plurality of banks. The memory die may further include a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die may further include a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit may be located under the footprint of the array and the second ECC circuit may be located outside the footprint of the array.
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Patent Agency Ranking
公开(公告)号：US20200177184A1
公开(公告)日：2020-06-04
申请号：US16205953
申请日：2018-11-30
Applicant: Micron Technology, Inc.
Inventor： Hiroshi Akamatsu , Ki-Jun Nam , John David Porter
IPC: H03K19/00 , H03K19/096
Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).
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公开(公告)号：US20160172018A1
公开(公告)日：2016-06-16
申请号：US14571735
申请日：2014-12-16
Applicant: Micron Technology, Inc.
Inventor： Ki-Jun Nam , John David Porter
CPC classification number: G11C7/1012 , G11C7/00 , G11C7/10 , G11C7/106 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C8/00 , G11C8/18 , G11C2207/107 , H03K3/017 , H03K5/1502 , H03L7/06
Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.
Abstract translation: 描述了使用分时钟捕获数据的装置和方法。 示例性装置包括被配置为接收DQS信号并且提供分频时钟信号的时钟分配器。 分频时钟信号的分频时钟信号的频率小于DQS信号的频率。 该示例设备还包括命令电路，其被配置为接收命令，并且基于所划分的时钟信号以及从接收到该命令的时间开始确定的延迟来断言多个标志信号之一。 该示例设备还包括数据捕获电路，其配置为串行地接收与该命令相关联的数据，并且响应于划分的时钟信号提供反序列化数据。 数据捕获电路还被配置为基于所述多个标志信号中的所述一个标记信号对反序列化数据进行排序以提供分类数据。
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28.发明授权公开(公告)号：US08861296B2
公开(公告)日：2014-10-14
申请号：US14084417
申请日：2013-11-19
Applicant: Micron Technology, Inc.
Inventor： John David Porter , Gi-Hong Kim
IPC: G11C7/00 , G11C11/402 , G11C11/408 , G11C8/08 , G11C5/14 , G11C11/406 , G11C8/10
CPC classification number: G11C11/40615 , G11C5/147 , G11C8/08 , G11C8/10 , G11C11/402 , G11C11/406 , G11C11/4085 , G11C2211/4065 , G11C2211/4067
Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
Abstract translation: 公开了设备，存储器部分控制电路和刷新存储器的方法。 示例性设备包括多个存储器部分和多个存储器部分控制电路。 每个存储器部分控制电路耦合到多个存储器部分中的相应一个，并且包括多个存取线驱动器，每个存取线驱动器包括具有公共耦合栅极的多个晶体管。 在装置的操作期间，将第一电压提供给耦合到有源存储器部分的存储器部分控制电路的至少一些存取线驱动器的晶体管的共同耦合的栅极，并且第二电压被提供给共同耦合的 存储器部分控制电路的存取线驱动器的晶体管的栅极耦合到非活动存储器部分控制电路，其中第一电压大于第二电压。
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公开(公告)号：US20250147858A1
公开(公告)日：2025-05-08
申请号：US19016045
申请日：2025-01-10
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti , John David Porter
Abstract: Systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. A system may include a memory device and a memory controller communicatively coupled to the memory device. The memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. The memory controller may perform a memory management operation based on the memory management interval. Sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.
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公开(公告)号：US20240363192A1
公开(公告)日：2024-10-31
申请号：US18761619
申请日：2024-07-02
Applicant: Micron Technology, Inc.
Inventor： Alan John Wilson , Donald M. Morgan , John David Porter
CPC classification number: G11C29/76 , G11C29/54 , G11C29/808
Abstract: Apparatus and methods for page-based soft post package repair are disclosed. Based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. A match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. A decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. A page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.
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