公开(公告)号：US20240087625A1

公开(公告)日：2024-03-14

申请号：US17942944

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Kari Crane ,  Kevin G. Werhane ,  Yoshinori Fujiwara ,  Jason M. Johnson ,  Takuya Tamano ,  Daniel S. Miller

IPC: G11C7/24 ,  G11C7/10 ,  G11C17/16

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1063 ,  G11C17/16

Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.

公开(公告)号：US20230223059A1

公开(公告)日：2023-07-13

申请号：US17575378

申请日：2022-01-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Hiroshi Akamatsu ,  Jian Long ,  Kevin G. Werhane ,  Liang Liu ,  Yoshinori Fujiwara

IPC: G11C7/10

CPC classification number: G11C7/1087

Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.

公开(公告)号：US11342042B2

公开(公告)日：2022-05-24

申请号：US16836646

申请日：2020-03-31

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Yoshinori Fujiwara ,  Kevin G. Werhane

IPC: G11C29/30 ,  G11C29/48 ,  H01L25/065 ,  G11C5/06 ,  H01L23/538 ,  G11C8/06

Abstract: Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

公开(公告)号：US20210304838A1

公开(公告)日：2021-09-30

申请号：US16836646

申请日：2020-03-31

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Yoshinori Fujiwara ,  Kevin G. Werhane

IPC: G11C29/48 ,  H01L25/065 ,  G11C8/06 ,  H01L23/538 ,  G11C5/06

Abstract: Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

公开(公告)号：US10663513B2

公开(公告)日：2020-05-26

申请号：US16416242

申请日：2019-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kevin G. Werhane ,  Nathaniel J. Meier ,  Bin Liu

IPC: G01R31/307 ,  G01R31/30 ,  H03L7/081 ,  H03K5/133 ,  H01J37/26 ,  G01R31/28 ,  G01R31/26 ,  G01R31/50

Abstract: Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.

公开(公告)号：US20190271739A1

公开(公告)日：2019-09-05

申请号：US16416242

申请日：2019-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kevin G. Werhane ,  Nathaniel J. Meier ,  Bin Liu

IPC: G01R31/307 ,  H03K5/133 ,  G01R31/30 ,  H03L7/081 ,  H01J37/26

Abstract: Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.

公开(公告)号：US10330726B2

公开(公告)日：2019-06-25

申请号：US15626941

申请日：2017-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kevin G. Werhane ,  Nathaniel J. Meier ,  Bin Liu

IPC: G01R31/26 ,  G01R31/307 ,  G01R31/30 ,  H03L7/081 ,  H03K5/133 ,  H01J37/26

Abstract: Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.