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    Leakage current reduction in electronic devices
    21.
    发明授权
    Leakage current reduction in electronic devices 有权

    公开(公告)号：US11658662B2

    公开(公告)日：2023-05-23

    申请号：US17078965

    申请日：2020-10-23

    Applicant: Micron Technology, inc.

    Inventor： Hiroshi Akamatsu ,  Ki-Jun Nam ,  John David Porter

    IPC: H03K19/00 ,  H03K19/096

    CPC classification number: H03K19/0016 ,  H03K19/0963

    Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

    Boundary protection in memory
    22.
    发明授权
    Boundary protection in memory 有权

    公开(公告)号：US11615828B2

    公开(公告)日：2023-03-28

    申请号：US17524514

    申请日：2021-11-11

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  Hiroshi Akamatsu ,  Takamasa Suzuki ,  Yasushi Matsubara

    IPC: G11C11/22 ,  G11C11/4074 ,  G06F11/30 ,  G11C5/14

    Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

    SEQUENTIAL VOLTAGE CONTROL FOR A MEMORY DEVICE
    23.
    发明申请
    SEQUENTIAL VOLTAGE CONTROL FOR A MEMORY DEVICE 有权

    公开(公告)号：US20220246219A1

    公开(公告)日：2022-08-04

    申请号：US17675622

    申请日：2022-02-18

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

    IPC: G11C16/30 ,  G11C16/12 ,  G11C7/20 ,  G11C16/04 ,  G11C16/32 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/417

    Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

    DC voltage regulators with demand-driven power management
    25.
    发明授权
    DC voltage regulators with demand-driven power management 有权

    公开(公告)号：US11226646B2

    公开(公告)日：2022-01-18

    申请号：US16891963

    申请日：2020-06-03

    Applicant: Micron Technology, Inc.

    Inventor： Si Hong Kim ,  Ki-Jun Nam

    IPC: G05F1/613 ,  G11C11/4074 ,  H02M3/158 ,  G06F1/26 ,  G11C11/22 ,  H02M1/00

    Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.

    Regulators with offset voltage cancellation
    26.
    发明授权
    Regulators with offset voltage cancellation 有权

    公开(公告)号：US10996694B2

    公开(公告)日：2021-05-04

    申请号：US16448162

    申请日：2019-06-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ki-Jun Nam ,  John David Porter

    IPC: G05F1/44 ,  H02M7/537 ,  H02M1/00 ,  H03F3/45 ,  H03M1/10

    Abstract: A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.

    LEAKAGE CURRENT REDUCTION IN ELECTRONIC DEVICES
    28.
    发明申请
    LEAKAGE CURRENT REDUCTION IN ELECTRONIC DEVICES 有权

    公开(公告)号：US20210044296A1

    公开(公告)日：2021-02-11

    申请号：US17078965

    申请日：2020-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Hiroshi Akamatsu ,  Ki-Jun Nam ,  John David Porter

    IPC: H03K19/00 ,  H03K19/096

    Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

    Apparatuses and methods for capturing data using a divided clock
    29.
    发明授权
    Apparatuses and methods for capturing data using a divided clock 有权
    使用分时钟捕获数据的设备和方法

    公开(公告)号：US09524759B2

    公开(公告)日：2016-12-20

    申请号：US14571735

    申请日：2014-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  John David Porter

    IPC: G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G11C7/10 ,  H03K5/15 ,  G11C7/22 ,  H03K3/017 ,  G11C7/00 ,  G11C8/00 ,  H03L7/06 ,  G11C8/18

    CPC classification number: G11C7/1012 ,  G11C7/00 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/00 ,  G11C8/18 ,  G11C2207/107 ,  H03K3/017 ,  H03K5/1502 ,  H03L7/06

    Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.

    Abstract translation: 描述了使用分时钟捕获数据的装置和方法。 示例性装置包括被配置为接收DQS信号并且提供分频时钟信号的时钟分配器。 分频时钟信号的分频时钟信号的频率小于DQS信号的频率。 该示例设备还包括命令电路，其被配置为接收命令，并且基于所划分的时钟信号以及从接收到该命令的时间开始确定的延迟来断言多个标志信号之一。 该示例设备还包括数据捕获电路，其配置为串行地接收与该命令相关联的数据，并且响应于划分的时钟信号提供反序列化数据。 数据捕获电路还被配置为基于所述多个标志信号中的所述一个标记信号对反序列化数据进行排序以提供分类数据。

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