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公开(公告)号：US12014778B2
公开(公告)日：2024-06-18
申请号：US17670037
申请日：2022-02-11
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang , Tomoko Ogura Iwasaki
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.
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公开(公告)号：US20240177755A1
公开(公告)日：2024-05-30
申请号：US18388032
申请日：2023-11-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jeffrey S. McNeil , Eric N. Lee , Tomoko Ogura Iwasaki , Sheyang Ning , Lawrence Celso Miranda , Kishore Kumar Muchherla
CPC classification number: G11C11/005 , G06F12/0246 , G11C16/0483
Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells
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公开(公告)号：US11887668B2
公开(公告)日：2024-01-30
申请号：US17669074
申请日：2022-02-10
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and applies, during a first time period of the program operation, a ramping wordline voltage to a set of wordlines associated with the memory array. The control logic causes, during the first time period, a disconnection of a set of pillars associated with the set of memory cells from a voltage supply and ground voltage, wherein each pillar corresponds to a programming level of a set of programming levels. The control logic further causes, during a second time period of the program operation, a set of programming pulses to be applied to the set of memory cells, wherein each programming pulse of the set of programming pulses programs each programming level of the set of programming levels associated with the identified set of memory cells.
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公开(公告)号：US20240029809A1
公开(公告)日：2024-01-25
申请号：US18376198
申请日：2023-10-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Ting Luo , Luyen Vu
CPC classification number: G11C29/42 , G11C29/4401 , G11C7/1096 , G11C7/1069 , G11C29/12005
Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.
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公开(公告)号：US20230307055A1
公开(公告)日：2023-09-28
申请号：US18121846
申请日：2023-03-15
Applicant: Micron Technology, Inc.
Inventor： Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Sheyang Ning , Jeffrey S. McNeil
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26
Abstract: Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and one or more target bitlines; causing a first programming pulse to be performed by applying a first programming voltage to the target wordline; classifying, by a processing device, the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a second programing voltage to be applied to the target wordline, wherein the second programming voltage exceeds the first programing voltage.
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Patent Agency Ranking
公开(公告)号：US11742034B2
公开(公告)日：2023-08-29
申请号：US17745415
申请日：2022-05-16
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Lawrence Celso Miranda
CPC classification number: G11C16/3404 , G11C16/10 , G11C16/26 , G11C16/30
Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.
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公开(公告)号：US20230207018A1
公开(公告)日：2023-06-29
申请号：US18077681
申请日：2022-12-08
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang
CPC classification number: G11C16/102 , G11C16/16 , G11C16/0433 , G11C16/3459
Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a selected wordline associated with a set of memory cells to be programmed to a target voltage level representing a programming level. Voltage levels of the selected wordline and one or more unselected wordlines of the memory array are discharged to approximately a ground voltage level and a bitline voltage level is applied to a bitline corresponding to the programming level. The selected wordline and a set of unselected wordlines are charged to approximately a pass voltage level followed by the discharge of the selected wordline to a reverse bias level to establish an erase voltage level on the set of memory cells. The control logic further performs a program verify operation corresponding to the programming level associated with the set of memory cells.
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公开(公告)号：US20220375525A1
公开(公告)日：2022-11-24
申请号：US17324538
申请日：2021-05-19
Applicant: Micron Technology, Inc.
Inventor： Tomoko Ogura Iwasaki , Kulachet Tanpairoj , Jianmin Huang , Lawrence Celso Miranda , Sheyang Ning
Abstract: Described are systems and methods for performing memory programming operations in the overwrite mode. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: responsive to identifying a first data item to be stored by a portion of the memory array, causing a first memory programming operation to be performed to program, to a first target threshold voltage, a set of memory cells comprised by the portion of the memory array; and responsive to identifying a second data item to be stored by the portion of the memory array, causing a second memory programming operation to be performed to program the set of memory cells to a second target threshold voltage exceeding the first target threshold voltage.
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公开(公告)号：US20220310166A1
公开(公告)日：2022-09-29
申请号：US17670037
申请日：2022-02-11
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang , Tomoko Ogura Iwasaki
Abstract: Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.
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公开(公告)号：US12254927B2
公开(公告)日：2025-03-18
申请号：US18654697
申请日：2024-05-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang , Tomoko Ogura Iwasaki
Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.
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