公开(公告)号：US11836096B2

公开(公告)日：2023-12-05

申请号：US17559320

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Robert Walker ,  Laurent Isenegger

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/30

CPC classification number: G06F13/1668 ,  G06F9/30101 ,  G06F13/1621 ,  G06F13/1642 ,  G06F13/4221

Abstract: Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.

公开(公告)号：US20230161507A1

公开(公告)日：2023-05-25

申请号：US18095878

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0673 ,  G06F3/0604

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US20230053291A1

公开(公告)日：2023-02-16

申请号：US17975164

申请日：2022-10-27

Applicant: Micron Technology. Inc/

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F12/06 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/33 ,  H04W4/029 ,  H04W4/02

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US11580039B2

公开(公告)日：2023-02-14

申请号：US17099309

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Robert Walker

IPC: G06F13/16 ,  G06F12/06 ,  G06F12/10

Abstract: Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.

公开(公告)号：US11507504B2

公开(公告)日：2022-11-22

申请号：US17204522

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F13/00 ,  G06F12/06 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/33 ,  H04W4/029 ,  H04W4/02 ,  G06F9/30 ,  H04B17/24 ,  H04W84/12 ,  H04L101/622 ,  H04L101/69

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US20220027095A1

公开(公告)日：2022-01-27

申请号：US17498415

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

公开(公告)号：US11163486B2

公开(公告)日：2021-11-02

申请号：US16694427

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Dhawal Bavishi ,  Robert Walker

IPC: G06F3/06

Abstract: Various embodiments described herein provide for execution of a memory function within a memory sub-system. For example, some embodiments provide for execution of certain memory-related functions internally within the memory sub-system, at the request of a host system, using one or more memory access operations (e.g., direct memory access operations) performed internally within the memory sub-system.

公开(公告)号：US20190121723A1

公开(公告)日：2019-04-25

申请号：US16126405

申请日：2018-09-10

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  David A. Roberts

IPC: G06F12/02 ,  G06F3/06 ,  G06F1/20 ,  G06F1/3234 ,  G06F12/122 ,  G06F13/24 ,  G06F13/42 ,  G06F13/16 ,  G11C7/04

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

公开(公告)号：US20180322039A1

公开(公告)日：2018-11-08

申请号：US16030600

申请日：2018-07-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

IPC: G06F12/02 ,  G06F13/16

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

公开(公告)号：US10089221B2

公开(公告)日：2018-10-02

申请号：US14247833

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  David A. Roberts

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/12 ,  G06F13/28 ,  G06F12/02 ,  G06F3/06 ,  G06F12/122 ,  G06F13/24 ,  G11C7/04 ,  G06F1/20 ,  G06F1/32 ,  G06F13/16 ,  G06F13/42 ,  G11C11/406

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.