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    Enhanced performance memory systems and methods
    22.
    发明授权
    Enhanced performance memory systems and methods 有权
    增强的性能内存系统和方法

    公开(公告)号：US09154131B2

    公开(公告)日：2015-10-06

    申请号：US13796410

    申请日：2013-03-12

    Applicant: Micron Technology, Inc.

    Inventor： Roy E. Greeff ,  David K. Ovard

    IPC: G11C5/06 ,  H03K19/003 ,  G06F13/40

    CPC classification number: H03K19/003 ,  G06F13/4086

    Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.

    Abstract translation: 公开了包括用于操作这种存储器系统的存储器系统和方法的数字存储器件和系统。 在实施例中，存储器系统可以包括通信地耦合到处理器的处理器和存储器控制器。 存储器总线通过存储器总线与至少两个存储器单元进行通信。 至少一个除法器单元可以插入在存储器总线和至少两个存储器单元之间，该至少两个存储器单元被配置为在将存储器总线的阻抗与存储器单元的阻抗匹配的同时大致相等地分配接收信号的电平。

    APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES
    24.
    发明公开
    APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240063188A1

    公开(公告)日：2024-02-22

    申请号：US18499087

    申请日：2023-10-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

    IPC: H01L25/065 ,  H01L25/18

    CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

    Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.

    Memory subsystem register clock driver clock teeing
    25.
    发明授权
    Memory subsystem register clock driver clock teeing 有权

    公开(公告)号：US11468931B2

    公开(公告)日：2022-10-11

    申请号：US17360964

    申请日：2021-06-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

    IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

    Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.

    CONFIGURING MULTIPLE REGISTER CLOCK DRIVERS OF A MEMORY SUBSYSTEM
    26.
    发明申请
    CONFIGURING MULTIPLE REGISTER CLOCK DRIVERS OF A MEMORY SUBSYSTEM 有权

    公开(公告)号：US20220004517A1

    公开(公告)日：2022-01-06

    申请号：US17360994

    申请日：2021-06-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

    IPC: G06F13/42 ,  G06F13/16 ,  G06F1/08 ,  G11C8/18 ,  G11C8/06

    Abstract: Methods, systems, and apparatuses related to configured dual register clock driver (RCD) devices on a single memory subsystem using different configuration information are described. In some examples, configuration of the two RCD devices with different configuration information may include use of a serial data bus to receive and store first RCD configuration data, which is provided to both of the RCD devices to configure one or more parameters of each respective RCD device. One of the RCD devices may receive second configuration data via a command and address bus to independently update the one or more configuration parameters of one of the two RCD devices.

    MEMORY DEVICE INTERFACE AND METHOD
    27.
    发明申请
    MEMORY DEVICE INTERFACE AND METHOD 审中-公开

    公开(公告)号：US20200272560A1

    公开(公告)日：2020-08-27

    申请号：US16797618

    申请日：2020-02-21

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

    IPC: G06F12/02 ,  H01L25/065

    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

    Apparatuses and methods for partial bit de-emphasis
    29.
    发明授权
    Apparatuses and methods for partial bit de-emphasis 有权

    公开(公告)号：US10340913B2

    公开(公告)日：2019-07-02

    申请号：US16130900

    申请日：2018-09-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Roy E. Greeff

    IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0185 ,  H03K5/1534 ,  H04L25/02

    Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.

    Memory device interface and method
    30.
    发明授权
    Memory device interface and method 有权

    公开(公告)号：US12277056B2

    公开(公告)日：2025-04-15

    申请号：US18215474

    申请日：2023-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

    IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

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