公开(公告)号：US11923001B2

公开(公告)日：2024-03-05

申请号：US17580178

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/34 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

公开(公告)号：US20230206997A1

公开(公告)日：2023-06-29

申请号：US17580178

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

公开(公告)号：US20230206992A1

公开(公告)日：2023-06-29

申请号：US18083077

申请日：2022-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Junwyn A. Lacsao ,  Jeffrey S. McNeil ,  Violante Moschiano ,  Paing Z. Htet ,  Sead Zildzic ,  Eric N. Lee

IPC: G11C11/4091 ,  G11C11/4099 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G11C11/4093 ,  G11C11/4099

Abstract: Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.

公开(公告)号：US20230197163A1

公开(公告)日：2023-06-22

申请号：US18076488

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Akira Goda ,  Jonathan S. Parry ,  Violante Moschiano

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/28

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

公开(公告)号：US11231982B2

公开(公告)日：2022-01-25

申请号：US17248538

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Jung Sheng Hoei ,  Peter Sean Feeley ,  Sampath K. Ratnam ,  Sead Zildzic ,  Kishore Kumar Muchherla

IPC: G06F11/00 ,  G06F11/07 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

Abstract: A processing device in a memory system incrementally adjusts a center read voltage for a first block of a memory device by a first offset amount to generate an adjusted read voltage and causes the adjusted read voltage to be applied to the first block to determine an adjusted bit count associated with the adjusted read voltage. The processing device further determines whether a difference between the adjusted bit count and a previous bit count associated with a previous read voltage satisfies a first threshold criterion pertaining to an error threshold, and responsive to the difference between the adjusted bit count and the previous bit count not satisfying the first threshold criterion, determines a read window for the first block based on the previous read voltage.

公开(公告)号：US20210149755A1

公开(公告)日：2021-05-20

申请号：US17248538

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Jung Sheng Hoei ,  Peter Sean Feeley ,  Sampath K. Ratnam ,  Sead Zildzic ,  Kishore Kumar Muchherla

IPC: G06F11/07 ,  G11C16/34 ,  G11C16/26

Abstract: A processing device in a memory system incrementally adjusts a center read voltage for a first block of a memory device by a first offset amount to generate an adjusted read voltage and causes the adjusted read voltage to be applied to the first block to determine an adjusted bit count associated with the adjusted read voltage. The processing device further determines whether a difference between the adjusted bit count and a previous bit count associated with a previous read voltage satisfies a first threshold criterion pertaining to an error threshold, and responsive to the difference between the adjusted bit count and the previous bit count not satisfying the first threshold criterion, determines a read window for the first block based on the previous read voltage.