公开(公告)号：US12282682B2

公开(公告)日：2025-04-22

申请号：US18415285

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US20250006251A1

公开(公告)日：2025-01-02

申请号：US18829647

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Glen E. Hush ,  Sean S. Eilert ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

公开(公告)号：US20240419549A1

公开(公告)日：2024-12-19

申请号：US18821203

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: G06F11/10

Abstract: Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.

公开(公告)号：US12073110B2

公开(公告)日：2024-08-27

申请号：US17931262

申请日：2022-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G06F12/00 ,  C12Q1/6869 ,  G06F3/06

CPC classification number: G06F3/0655 ,  C12Q1/6869 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

公开(公告)号：US12045503B2

公开(公告)日：2024-07-23

申请号：US17515229

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivam Swami ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G06F12/02 ,  H10B63/00

CPC classification number: G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  H10B63/84 ,  G06F3/0622

Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.

公开(公告)号：US12008460B2

公开(公告)日：2024-06-11

申请号：US17007588

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

CPC classification number: G06N3/063 ,  G06N3/049 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

公开(公告)号：US20240087643A1

公开(公告)日：2024-03-14

申请号：US17931277

申请日：2022-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G11C13/00 ,  C12Q1/6869 ,  G11C7/16 ,  G16B30/10

CPC classification number: G11C13/0069 ,  C12Q1/6869 ,  G11C7/16 ,  G11C13/004 ,  G16B30/10

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

公开(公告)号：US20230208444A1

公开(公告)日：2023-06-29

申请号：US17677593

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: H03M13/15 ,  H03M13/43 ,  G11C15/04 ,  G06F11/10

CPC classification number: H03M13/1575 ,  G06F11/1068 ,  G11C15/04 ,  H03M13/43

Abstract: Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.

公开(公告)号：US20230065783A1

公开(公告)日：2023-03-02

申请号：US17647944

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Justin Eno ,  Brian Hirano

IPC: G06F3/06

Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

公开(公告)号：US20230051863A1

公开(公告)日：2023-02-16

申请号：US17712935

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C11/4091 ,  G11C11/408

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.