公开(公告)号：US20210257226A1

公开(公告)日：2021-08-19

申请号：US17227525

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US11004697B2

公开(公告)日：2021-05-11

申请号：US16436461

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US10763131B2

公开(公告)日：2020-09-01

申请号：US15817000

申请日：2017-11-17

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US10679921B2

公开(公告)日：2020-06-09

申请号：US16162012

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L21/00 ,  H01L23/02 ,  H01L23/367 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Vias may directly electrically connect the uppermost semiconductor die to the substrate.

公开(公告)号：US20190157111A1

公开(公告)日：2019-05-23

申请号：US15817000

申请日：2017-11-17

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US20190051578A1

公开(公告)日：2019-02-14

申请号：US16162012

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/48 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Vias may directly electrically connect the uppermost semiconductor die to the substrate.

公开(公告)号：US10170389B2

公开(公告)日：2019-01-01

申请号：US14825009

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L23/36 ,  H01L25/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20180033781A1

公开(公告)日：2018-02-01

申请号：US15728123

申请日：2017-10-09

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L25/18 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

公开(公告)号：US09865578B2

公开(公告)日：2018-01-09

申请号：US14730681

申请日：2015-06-04

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L29/40 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

公开(公告)号：US09070656B2

公开(公告)日：2015-06-30

申请号：US13915778

申请日：2013-06-12

Applicant: Micron Technology, Inc.

Inventor： Andy E. Hooper ,  Xiao Li ,  Shijian Luo

IPC: H01L23/34 ,  H01L23/36 ,  H01L23/10 ,  H01L23/367 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/36 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/4275 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/16251 ,  H01L2924/00

Abstract: Heat spreaders for dissipating heat from semiconductor devices comprise a contact surface located within a recess on an underside of the heat spreader, the contact surface being configured to physically and thermally attach to a semiconductor device, and a trench extending into the heat spreader adjacent to the contact surface sized and configured to receive underfill material extending from the semiconductor device into the trench. Related semiconductor device assemblies may include these heat spreaders and methods may include physically and thermally attaching these heat spreaders to semiconductor devices such that underfill material extends from a semiconductor device into the trench.

Abstract translation: 用于从半导体器件散热的散热器包括位于散热器下侧的凹部内的接触表面，该接触表面构造成物理地和热连接到半导体器件，以及延伸到与散热器相邻的散热器中的沟槽 接触表面的尺寸和构造以接收从半导体器件延伸到沟槽中的底部填充材料。 相关的半导体器件组件可以包括这些散热器，并且方法可以包括将这些散热器物理地和热连接到半导体器件，使得底部填充材料从半导体器件延伸到沟槽中。