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公开(公告)号：US10566063B2
公开(公告)日：2020-02-18
申请号：US15981810
申请日：2018-05-16
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: determine a set of read results based on reading a subset of memory cells according to read levels maintained within optimization trim data, wherein the optimization trim data initially comprises at least one read level in addition to a target trim; calibrate the set of read levels based on the set of read results; and remove the calibrated read levels from the optimization trim data when the calibrated read levels satisfy a calibration condition.
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公开(公告)号：US11842772B2
公开(公告)日：2023-12-12
申请号：US17857942
申请日：2022-07-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Sheperek , Bruce A. Liikanen , Steve Kientz
CPC classification number: G11C16/10 , G06F12/0246 , G06F12/0882 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3404 , G06F2212/7207 , G11C2207/2254
Abstract: A first bin boundary for a first voltage bin associated with a die of a memory device is identified. The first bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family is determined. The first bin boundary is updated based on the first bin boundary offset.
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公开(公告)号：US11721399B2
公开(公告)日：2023-08-08
申请号：US17504467
申请日：2021-10-18
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
CPC classification number: G11C16/26 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0483
Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to manage optimization target data that at least initially includes read levels in addition to a target trip, wherein the optimization data is managed based on iteratively calibrating the read levels and removing the calibrated levels from the optimization target data.
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公开(公告)号：US20220336021A1
公开(公告)日：2022-10-20
申请号：US17857942
申请日：2022-07-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Sheperek , Bruce A. Liikanen , Steve Kientz
Abstract: A first bin boundary for a first voltage bin associated with a die of a memory device is identified. The first bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family is determined. The first bin boundary is updated based on the first bin boundary offset.
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公开(公告)号：US11416173B2
公开(公告)日：2022-08-16
申请号：US16850224
申请日：2020-04-16
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A memory device includes a processing device configured to iteratively update a center read level according to a first step size after reading a subset of memory cells according to a set of read levels including the center read level; track an update direction for the processing device to use when iteratively updating the center read level, wherein the update direction corresponds to an increase or a decrease in the center read level; detect a change condition based on updating the center read level according to the first step size; and iteratively update the center read level according to a second step size based on detection of the change condition.
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Patent Agency Ranking
公开(公告)号：US20220084596A1
公开(公告)日：2022-03-17
申请号：US17022908
申请日：2020-09-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Sheperek , Bruce A. Liikanen , Steve Kientz
Abstract: A first current bin boundary for a first voltage bin on a first target die of a set of dies at a memory device is identified by accessing a block family metadata table including an entry for each block family of a memory device. The first current bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family corresponding to a first new bin boundary for the first voltage bin is determined. The first bin boundary is determined based on a calibration scan performed for the first voltage bin. A first new bin boundary for the first voltage bin is determined on each die of the set of dies based on the first bin boundary offset.
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公开(公告)号：US20200168282A1
公开(公告)日：2020-05-28
申请号：US16775099
申请日：2020-01-28
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: calibrate read levels based on associated read results, wherein the read levels are tracked via optimization target data that at least initially includes at least one read level in addition to a target trim; and remove a calibrated read level from the optimization target data when the calibrated read level satisfies a calibration condition.
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公开(公告)号：US20200005870A1
公开(公告)日：2020-01-02
申请号：US16566713
申请日：2019-09-10
Applicant: Micron Technology, Inc.
Inventor： Gerald L. Cadloni , Steve Kientz , Bruce A. Liikanen
Abstract: A system includes a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory locations of the memory device; and a processing device, operatively coupled to the memory device, to: determine whether a quantity of start voltage values in the set of start voltage values stored in the memory device meets a threshold; modify the set of start voltage values stored in the memory device to remove one or more start voltage values from the set in response to a determination that the quantity of start voltage values in the set meets the threshold; and add a new start voltage value to the modified set of start voltage values.
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公开(公告)号：US10482965B1
公开(公告)日：2019-11-19
申请号：US15967265
申请日：2018-04-30
Applicant: Micron Technology, Inc.
Inventor： Gerald L. Cadloni , Steve Kientz , Bruce A. Liikanen
Abstract: A system includes a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory locations of the memory device; and a processing device, operatively coupled to the memory device, to: determine whether a quantity of start voltage values in the set of start voltage values stored in the memory device meets a threshold; modify the set of start voltage values stored in the memory device to remove one or more start voltage values from the set in response to a determination that the quantity of start voltage values in the set meets the threshold; and add a new start voltage value to the modified set of start voltage values.
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公开(公告)号：US20190333582A1
公开(公告)日：2019-10-31
申请号：US15967265
申请日：2018-04-30
Applicant: Micron Technology, Inc.
Inventor： Gerald L. Cadloni , Steve Kientz , Bruce A. Liikanen
Abstract: A system includes a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory locations of the memory device; and a processing device, operatively coupled to the memory device, to: determine whether a quantity of start voltage values in the set of start voltage values stored in the memory device meets a threshold; modify the set of start voltage values stored in the memory device to remove one or more start voltage values from the set in response to a determination that the quantity of start voltage values in the set meets the threshold; and add a new start voltage value to the modified set of start voltage values.
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