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公开(公告)号：US20240256444A1
公开(公告)日：2024-08-01
申请号：US18411940
申请日：2024-01-12
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Guang Hu , Xianganfg Luo , Jung Sheng Hoei , Ting Luo , Zhenming Zhou , Jianmin Huang
IPC: G06F12/06
CPC classification number: G06F12/0607
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to generate virtual or superblocks using multiple partial good blocks. The controller identifies a first partial good block (PGB) in a set of memory components, the first PGB having first subset of word line groups (WGRs) that are categorized as being non-defective. The controller searches for a second PGB in the set of memory components having a second subset of WGRs that are categorized as being non-defective. The controller computes a total quantity of WGRs based on the first quantity of WGRs in the first subset of WGRs and a second quantity of WGRs in the second subset of WGRs and, in response, combines the first PGB and the second PGB to form an individual virtual block.
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公开(公告)号：US20240242752A1
公开(公告)日：2024-07-18
申请号：US18403468
申请日：2024-01-03
Applicant: Micron Technology, Inc.
Inventor： Christopher Joseph Bueb , Ting Luo , Luca Porzio , Gianluca Coppola , Ryan Laity
IPC: G11C11/406
CPC classification number: G11C11/40626 , G11C11/40615 , G11C11/40622
Abstract: Methods, systems, and devices for techniques for data refresh based on environmental conditions are described. A memory system may program data to a set of blocks, where an order in which the data be programmed to respective blocks of the set of blocks may be based on a first block ordering. The memory system may also program respective indications of respective temperatures of the programming for the respective blocks. The memory system may identify, during a start-up procedure, a flag indicating to perform a refresh operation for the set of blocks. As such, the memory system may perform during the start-up procedure, the refresh operation for the set of blocks using a second block ordering. In some examples, the second block ordering may be based on the respective indications of the respective temperatures for the set of blocks.
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公开(公告)号：US20240086079A1
公开(公告)日：2024-03-14
申请号：US18237668
申请日：2023-08-24
Applicant: Micron Technology, Inc.
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0634 , G06F3/0679
Abstract: A system comprises a memory device including a plurality of management units and a processing device. The processing device is operatively coupled with the memory device and configured to place the plurality of management units into a first protective state by erasing the plurality of management units, identify a cursor satisfying a cursor definition, identify a subset of the plurality of management units based on a location, on the memory device, referenced by the cursor, and place a selected management unit of the subset of the plurality of management units into a second protective state by programming a protective data pattern to the selected management unit.
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公开(公告)号：US20230176789A1
公开(公告)日：2023-06-08
申请号：US18103857
申请日：2023-01-31
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Xiangang Luo , Jianmin Huang , Phong S. Nguyen
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).
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公开(公告)号：US11657891B2
公开(公告)日：2023-05-23
申请号：US17743989
申请日：2022-05-13
Applicant: Micron Technology, Inc.
Inventor： Guang Hu , Ting Luo , Chun Sum Yueng
Abstract: A method includes determining whether a data reliability parameter associated with a set of memory cells is greater than a threshold data reliability parameter and in response to determining that the data reliability parameter is greater than the threshold data reliability parameter, performing an error recovery operation. The method further includes, subsequent to performing the error recovery operation, determining whether the data reliability parameter associated with the set of memory cells is less than the threshold data reliability parameter and in response to determining that the data reliability parameter is less than the threshold data reliability parameter, setting an offset associated with the error recovery operation as a default read voltage for the set of memory cells.
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Patent Agency Ranking
公开(公告)号：US11640346B2
公开(公告)日：2023-05-02
申请号：US17882975
申请日：2022-08-08
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Tao Liu , Christopher J. Bueb , Eric Yuen , Cheng Cheng Ang
Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.
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公开(公告)号：US11625298B2
公开(公告)日：2023-04-11
申请号：US17746754
申请日：2022-05-17
Applicant: Micron Technology, Inc.
Abstract: An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful. In response to a determination the program operation is unsuccessful, the memory block defect detection component is to determine that a failure involving a plane associated with the memory block and another plane of the memory sub-system has occurred.
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公开(公告)号：US11587613B2
公开(公告)日：2023-02-21
申请号：US17572209
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Sebastien Andre Jean , Ting Luo
Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.
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公开(公告)号：US11579797B2
公开(公告)日：2023-02-14
申请号：US17244290
申请日：2021-04-29
Applicant: Micron Technology, Inc.
Inventor： Tao Liu , Ting Luo , Jianmin Huang
Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.
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公开(公告)号：US20230043733A1
公开(公告)日：2023-02-09
申请号：US17395695
申请日：2021-08-06
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Xiangang Luo , Jianmin Huang , Phong S. Nguyen
IPC: G06F3/06
Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).
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