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    MULTILAYER CONNECTION STRUCTURE
    21.
    发明申请
    MULTILAYER CONNECTION STRUCTURE 审中-公开
    多层连接结构

    公开(公告)号：US20130161835A1

    公开(公告)日：2013-06-27

    申请号：US13772121

    申请日：2013-02-20

    Applicant: Macronix International Co., Ltd.

    Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

    IPC: H01L23/50

    CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

    Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

    Abstract translation: 三维堆叠IC器件包括在互连区域处的至少第一，第二，第三和第四接触电平的堆叠。 每个接触层具有导电层和绝缘层。 第一，第二，第三和第四电导体穿过接触层叠层的部分。 第一，第二，第三和第四电导体分别与第一，第二，第三和第四导电层电接触。 电介质侧壁间隔件周向地围绕第二，第三和第四电导体，使得第二，第三和第四电导体仅电相接触相应的第二，第三和第四导电层。

    Routing pattern
    22.
    发明授权
    Routing pattern 有权

    公开(公告)号：US12205894B2

    公开(公告)日：2025-01-21

    申请号：US17697074

    申请日：2022-03-17

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Cheng Yang ,  Yun-Chu Lin

    IPC: H01L23/528

    Abstract: A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.

    Memory device and manufacturing method thereof
    23.
    发明授权
    Memory device and manufacturing method thereof 有权

    公开(公告)号：US11901311B2

    公开(公告)日：2024-02-13

    申请号：US17390727

    申请日：2021-07-30

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chin-Cheng Yang

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

    CPC classification number: H01L23/562 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B43/27

    Abstract: A method of fabricating a memory device includes patterning a stacked structure to form a first staircase structure and a second staircase structure; patterning a conductive layer under the stacked structure to form a first slit trench along a first direction; forming a first dielectric layer overlaying the first staircase structure and the second staircase structure and filling into the first slit trench, wherein the first dielectric layer filled in the first slit trench forms a first slit; patterning the first dielectric layer, the stacked structure, and the conductive layer to form multiple second slit trenches, wherein the second slit trenches along a second direction perpendicular to the first direction; performing a replacement process to replace the sacrificial layers with multiple gate conductive layers; and filling a second dielectric layer in the second slit trenches to form multiple second slits.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    24.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20230033311A1

    公开(公告)日：2023-02-02

    申请号：US17390727

    申请日：2021-07-30

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chin-Cheng Yang

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

    Abstract: A method of fabricating a memory device includes patterning a stacked structure to form a first staircase structure and a second staircase structure; patterning a conductive layer under the stacked structure to form a first slit trench along a first direction; forming a first dielectric layer overlaying the first staircase structure and the second staircase structure and filling into the first slit trench, wherein the first dielectric layer filled in the first slit trench forms a first slit; patterning the first dielectric layer, the stacked structure, and the conductive layer to form multiple second slit trenches, wherein the second slit trenches along a second direction perpendicular to the first direction; performing a replacement process to replace the sacrificial layers with multiple gate conductive layers; and filling a second dielectric layer in the second slit trenches to form multiple second slits.

    MEMORY DEVICE AND FLASH MEMORY DEVICE
    25.
    发明申请
    MEMORY DEVICE AND FLASH MEMORY DEVICE 有权

    公开(公告)号：US20220406709A1

    公开(公告)日：2022-12-22

    申请号：US17350936

    申请日：2021-06-17

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chin-Cheng Yang

    IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A memory device includes a staircase structure, multiple first plugs, multiple second plugs, and multiple third plugs. The staircase structure includes multiple gate layers and multiple insulating layers alternately stacked on each other, and the staircase structure includes multiple first blocks and multiple second blocks which alternate with each other. The first plugs are disposed in the first blocks, and the first plugs in a same first block are staggered with each other. The second plugs are disposed in the first blocks. The second plugs in a same first block are staggered with each other, and the first plugs and the second plugs in a same first block are staggered with each other. The third plugs are disposed in the second blocks.

    Patterning method and semiconductor structure including forming a plurality of holes using line pattern masks
    30.
    发明授权
    Patterning method and semiconductor structure including forming a plurality of holes using line pattern masks 有权
    图案化方法和半导体结构，包括使用线图案掩模形成多个孔

    公开(公告)号：US09412615B2

    公开(公告)日：2016-08-09

    申请号：US14492969

    申请日：2014-09-22

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chin-Cheng Yang

    IPC: H01L21/4763 ,  H01L21/308 ,  H01L21/311

    CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32139

    Abstract: A patterning method is provided. A substrate including a material layer thereon is provided. A patterned hard mask layer, having a plurality of first holes, is formed on the material layer. Afterward, a mask layer, including a plurality of line pattern masks extending in a direction and dividing each first hole into a second hole and a third hole, is formed. The material layer is patterned using the patterned hard mask layer and the mask layer as masks to form a patterned material layer having a plurality of fourth and fifth holes. Furthermore, a semiconductor structure is provided.

    Abstract translation: 提供了图案化方法。 提供了包括其上的材料层的基板。 在材料层上形成具有多个第一孔的图案化的硬掩模层。 之后，形成包括在一个方向上延伸并将每个第一孔分成第二孔和第三孔的多个线图案掩模的掩模层。 使用图案化的硬掩模层和掩模层作为掩模来图案化材料层，以形成具有多个第四和第五孔的图案化材料层。 此外，提供了半导体结构。

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