公开(公告)号：US10120605B2

公开(公告)日：2018-11-06

申请号：US15093841

申请日：2016-04-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Yu-Ming Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

公开(公告)号：US09740602B2

公开(公告)日：2017-08-22

申请号：US14805498

申请日：2015-07-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

公开(公告)号：US09501396B2

公开(公告)日：2016-11-22

申请号：US13969462

申请日：2013-08-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Cheng-Yuan Wang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Pi-Cheng Hsiu ,  Tei-Wei Kuo

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/7204 ,  G06F2212/7211

Abstract: A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window. The method comprises, upon detection of a request to write a data object having a logical address mapped to a location outside the active window, updating the mapping so that the logical address maps to a selected location within the active window, and then allowing the write to the selected location. The method comprises maintaining access data indicating utilization of the plurality of address segments in the active window, and adding and removing address segments from the active window in response to the access data.

Abstract translation: 一种用于管理包括物理地址空间的存储器的利用的方法包括将数据对象的逻辑地址映射到物理地址空间内的位置，以及将空间中的多个地址段定义为活动窗口。 该方法包括允许将具有映射到活动窗口中的多个地址段内的位置的逻辑地址的数据对象的写入。 该方法包括在检测到写入具有映射到活动窗口之外的位置的逻辑地址的数据对象的请求时，更新映射，使得逻辑地址映射到活动窗口内的选定位置，然后允许写入 到所选位置。 该方法包括维护指示在活动窗口中多个地址段的利用的访问数据，以及响应于访问数据从活动窗口添加和移除地址段。

公开(公告)号：US20150178010A1

公开(公告)日：2015-06-25

申请号：US14523006

申请日：2014-10-24

Applicant: Macronix International Co., Ltd.

Inventor： Ping-Chun Chang ,  Yuan-Hao Chang ,  Hung-Sheng Chang ,  Tei-Wei Kuo ,  Hsiang-Pang Li

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0679 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1024 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/7201

Abstract: A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications. The plurality of physical memory segments is allocated to corresponding logical addresses based on the plurality of classifications, and on usage statistics of the physical memory segments. A data structure is maintained recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments. The plurality of classifications includes a first classification and a second classification having different usage statistic requirements than the first classification. Logical addresses having the second classification can be redirected to physical segments allocated to logical addresses having the first classification, and the data structure can be updated to record redirected logical addresses. A free command can release a physical memory segment allocated for main memory use.

Abstract translation: 提供了一种用于管理包括多个物理存储器段的存储器件的方法。 逻辑存储器空间根据使用规范被分类为多个分类。 基于多个分类，以及物理存储器段的使用统计，将多个物理存储器段分配给相应的逻辑地址。 数据结构保持在逻辑存储器空间中的逻辑地址和物理存储器段的物理地址之间进行记录转换。 多个分类包括与第一分类不同的使用统计要求的第一分类和第二分类。 具有第二分类的逻辑地址可以被重定向到分配给具有第一分类的逻辑地址的物理段，并且可以更新数据结构以记录重定向的逻辑地址。 免费命令可以释放分配给主内存使用的物理内存段。

公开(公告)号：US20140307505A1

公开(公告)日：2014-10-16

申请号：US14060296

申请日：2013-10-22

Applicant: Macronix International Co., Ltd

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。

公开(公告)号：US20140189276A1

公开(公告)日：2014-07-03

申请号：US13939948

申请日：2013-07-11

Applicant: Macronix International Co., Ltd.

Inventor： Hung-Sheng Chang ,  Cheng-Yuan Wang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Pi-Cheng Hsiu ,  Tei-Wei Kuo

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/7204 ,  G06F2212/7211

Abstract: A method is provided for managing a file system including data objects. The data objects, indirect pointers and source pointers are stored in containers that have addresses and include addressable units of a memory. The objects are mapped to addresses for corresponding containers. The indirect pointer in a particular container points to the address of a container in which the corresponding object is stored. The source pointer in the particular container points to the address of the container to which the object in the particular container is mapped. An object in a first container is moved to a second container. The source pointer in the first container is used to find a third container to which the object is mapped. The indirect pointer in the third container is updated to point to the second container. The source pointer in the second container is updated to point to the third container.

Abstract translation: 提供了一种用于管理包括数据对象的文件系统的方法。 数据对象，间接指针和源指针存储在具有地址并包含存储器可寻址单元的容器中。 对象映射到相应容器的地址。 特定容器中的间接指针指向存储相应对象的容器的地址。 特定容器中的源指针指向特定容器中的对象映射到的容器的地址。 将第一容器中的物体移动到第二容器。 第一个容器中的源指针用于查找对象映射到的第三个容器。 第三个容器中的间接指针被更新为指向第二个容器。 第二个容器中的源指针被更新为指向第三个容器。

公开(公告)号：US11966628B2

公开(公告)日：2024-04-23

申请号：US17830471

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Wang ,  Han-Wen Hu ,  Yung-Chun Li ,  Huai-Mu Wang ,  Chien-Chung Ho ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US11194515B2

公开(公告)日：2021-12-07

申请号：US16571249

申请日：2019-09-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ping-Hsien Lin ,  Wei-Chen Wang ,  Hsiang-Pang Li ,  Shu-Hsien Liao ,  Che-Wei Tsao ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G11C16/10

Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.

公开(公告)号：US20200319803A1

公开(公告)日：2020-10-08

申请号：US16742811

申请日：2020-01-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chen Wang ,  Ping-Hsien Lin ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G06F16/901 ,  G06F12/10

Abstract: A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.

公开(公告)号：US10108555B2

公开(公告)日：2018-10-23

申请号：US15370059

申请日：2016-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yuan-Hao Chang ,  Hsiu-Chang Chen ,  Tei-Wei Kuo

IPC: G06F12/02 ,  G06F12/121 ,  G06F12/00 ,  G06F12/06 ,  G06F12/1009

Abstract: A memory management method includes: providing a hybrid memory comprising a first type memory and a second type memory; providing an inactive list and a read active list for recording in-used pages on the first type memory; providing a write active list for recording in-used pages on the second type memory; allocating a page from the first type memory according to a system request, and inserting the page into the inactive list accordingly; moving the page from the inactive list to the write active list or the read active list in response to two or more successive access operations on the page; and referring the page to a physical address on the second type memory when the page is in the write active list.