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98 条记录 (耗时 0.036 秒)

    Display controller
    22.
    发明授权
    Display controller 失效
    显示控制器

    公开(公告)号：US06646651B1

    公开(公告)日：2003-11-11

    申请号：US09596044

    申请日：2000-06-16

    申请人： Koyo Katsura ,  Hideo Maejima ,  Hiroshi Takeda

    发明人： Koyo Katsura ,  Hideo Maejima ,  Hiroshi Takeda

    IPC分类号： G09G502

    CPC分类号： G09G5/36 ,  G09G5/363 ,  G09G5/39 ,  G09G5/397

    摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.

    摘要翻译： 在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性 通过将单位时钟分割成预定数量以高速功能和多功能显示。 当从与显示帧相对应的刷新存储器输入或输出图像数据时，存储器内容和显示地址以1：n的比例被分配以并行地进行处理。 结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示 。 所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。

    Graphic processing apparatus utilizing improved data transfer to reduce memory size
    23.
    再颁专利
    Graphic processing apparatus utilizing improved data transfer to reduce memory size 失效
    利用改进的数据传输来减少存储器大小的图形处理装置

    公开(公告)号：USRE37103E1

    公开(公告)日：2001-03-20

    申请号：US07985141

    申请日：1992-12-03

    申请人： Koyo Katsura ,  Shinichi Kojima ,  Noriyuki Kurakami

    发明人： Koyo Katsura ,  Shinichi Kojima ,  Noriyuki Kurakami

    IPC分类号： G06F1900

    CPC分类号： G09G5/393 ,  G06T1/60

    摘要： A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.

    摘要翻译： 存储器接口和视频属性控制器（MIVAC）插入在能够进行连续数据读取操作的动态RAM（DRAM）之间，诸如与静态列模式，页面模式或半字节模式相关联的操作，以及图形处理器 提供并行数据处理。 在MIVAC和DRAM之间的每个数据总线上执行串行数据传输，而在MIVAC和图形处理器之间进行并行数据传输。 结果，图形处理器可以被配置为具有减少数量的DRAM，使得图形处理器在不关注DRAM的连续数据读取模式的情况下操作。

    Display controller
    24.
    发明授权
    Display controller 失效
    显示控制器

    公开(公告)号：US6094193A

    公开(公告)日：2000-07-25

    申请号：US989390

    申请日：1997-12-12

    申请人： Koyo Katsura ,  Hideo Maejima ,  Hiroshi Takeda

    发明人： Koyo Katsura ,  Hideo Maejima ,  Hiroshi Takeda

    IPC分类号： G06F3/153 ,  G06F3/14 ,  G09G1/02 ,  G09G5/14 ,  G09G5/32 ,  G09G5/36 ,  G09G5/377 ,  G09G5/39 ,  G09G5/395 ,  G09G5/397 ,  G09G5/00 ,  G09G5/04

    CPC分类号： G09G5/36 ,  G09G5/363 ,  G09G5/39 ,  G09G5/397

    摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunctional display. When image data are to be inputted or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.

    摘要翻译： 在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性 通过将单位时钟分割成预定数量以高速功能和多功能显示。 当从与显示帧相对应的刷新存储器输入或输出图像数据时，存储器内容和显示地址以1：n的比例被分配以并行地进行处理。 结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示 。 所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。

    Graphic data processing system
    27.
    发明授权
    Graphic data processing system 失效
    图形数据处理系统

    公开(公告)号：US5448689A

    公开(公告)日：1995-09-05

    申请号：US234772

    申请日：1994-04-28

    申请人： Shigeru Matsuo ,  Koyo Katsura ,  Jun Sato ,  Takashi Sone ,  Masakatu Yokoyama

    发明人： Shigeru Matsuo ,  Koyo Katsura ,  Jun Sato ,  Takashi Sone ,  Masakatu Yokoyama

    IPC分类号： G06T17/00 ,  G06F15/62

    CPC分类号： G06T17/00

    摘要： A graphic processor which controls reading, writing and transfer of graphic data for a display memory that stores graphic data. The processor includes a first unit which stores first address information for addressing the display memory and first pixel address information which points a pixel position in a word specified by the first address information, a second unit which stores second address information for addressing the display memory and second pixel address information which points a pixel position in a word specified by the second address information, a third unit which shifts graphic data of multiple pixels included in two consecutive words to extract continuous 1-word graphic data, and a fourth unit which implements drawing computations pixel-wise concurrently for one word depending on the number of pixels included in a word. Even if transfer source graphic data lies across two consecutive words, the processor fetches the source data in single reading, processes the data word-wise at once, and stores the result in the display memory.

    摘要翻译： 用于控制用于存储图形数据的显示存储器的图形数据的读取，写入和传送的图形处理器。 处理器包括第一单元，其存储用于寻址显示存储器的第一地址信息和指向由第一地址信息指定的字中的像素位置的第一像素地址信息;第二单元，存储用于寻址显示存储器的第二地址信息;以及 指定由第二地址信息指定的字中的像素位置的第二像素地址信息;移动包括在两个连续字中的多个像素的图形数据以提取连续的1字图形数据的第三单元;以及实现图形的第四单元 根据包含在一个单词中的像素数量，对一个单词进行像素同步的计算。 即使传输源图形数据位于两个连续的字中，处理器以单次读取的方式读取源数据，一次处理数据，并将结果存储在显示存储器中。

    Data processing apparatus with clock signal control by microinstruction for reduced power consumption and method therefor
    28.
    发明授权
    Data processing apparatus with clock signal control by microinstruction for reduced power consumption and method therefor 失效
    具有通过微指令控制时钟信号的数据处理装置，用于降低功耗及其方法

    公开(公告)号：US4615005A

    公开(公告)日：1986-09-30

    申请号：US632820

    申请日：1984-07-20

    申请人： Hideo Maejima ,  Koyo Katsura ,  Toshimasa Kihara ,  Yasushi Akao

    发明人： Hideo Maejima ,  Koyo Katsura ,  Toshimasa Kihara ,  Yasushi Akao

    IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F9/30 ,  G06F11/00 ,  G06F7/38

    CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/324 ,  Y02B60/1217

    摘要： Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.

    摘要翻译： 公开了一种控制向逻辑电路提供时钟信号的方法，特别是由用于进一步降低功耗的C-MOS门组成的逻辑电路。 根据控制方法，存储时钟信号供给禁止指令，使得当读出该指令时，禁止向逻辑电路提供时钟信号，或者将其电平固定在特定信号电平。 响应于中断信号的应用，被禁止提供给逻辑电路的时钟信号开始再次提供给逻辑电路。 为了控制，可以自由地选择要禁止提供时钟信号的电路区域。 因此，当期望密切控制逻辑电路消耗的功率的节省时，该方法特别有效。

    Graphic processing apparatus and method
    30.
    发明授权
    Graphic processing apparatus and method 失效
    图形处理装置及方法

    公开(公告)号：US07019751B2

    公开(公告)日：2006-03-28

    申请号：US10636769

    申请日：2003-08-08

    申请人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

    发明人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

    IPC分类号： G09G5/39

    CPC分类号： G06F3/14 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/127

    摘要： A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

    摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，并且缓冲装置用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。