公开(公告)号：US20050223201A1

公开(公告)日：2005-10-06

申请号：US11095644

申请日：2005-03-30

申请人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

发明人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

摘要： One embodiment of the present invention provides a processor that facilitates rapid progress while speculatively executing instructions in scout mode. During normal operation, the processor executes instructions in a normal execution mode. Upon encountering a stall condition, the processor executes the instructions in a scout mode, wherein the instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. While speculatively executing the instructions in scout mode, the processor maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. If an instruction to be executed in scout mode depends on an unresolved data dependency, the processor executes the instruction as a NOOP so that the instruction executes rapidly without tying up computational resources. The processor also propagates dependency information indicating an unresolved data dependency to a destination register for the instruction.

摘要翻译： 本发明的一个实施例提供了一种在侦察模式下推测性地执行指令时促进快速进展的处理器。 在正常操作期间，处理器以正常执行模式执行指令。 在遇到停顿状态时，处理器以侦察模式执行指令，其中推测性地执行指令以预取将来的负载，但是其中结果未被提交到处理器的架构状态。 当在侦察模式中推测性地执行指令时，处理器维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 如果以侦察模式执行的指令取决于未解决的数据依赖关系，则处理器将该指令执行为NOOP，以使指令快速执行，而不占用计算资源。 处理器还将指示未解决的数据依赖关系的依赖信息传播到指令的目的地寄存器。

公开(公告)号：US20050223194A1

公开(公告)日：2005-10-06

申请号：US11082282

申请日：2005-03-16

申请人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

发明人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30061 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842

摘要： A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.

摘要翻译： 为用户提供了通过软件对存储器层次结构进行抽样的方法。 这允许用户通过软件来增强内存级并行性。 响应于第一计算机程序指令的执行，读取执行第二计算机程序指令所需的信息的状态。 在状态为第一状态时，继续执行第二计算机程序指令。 或者，在状态是与第一状态不同的第二状态的情况下执行第三计算机程序指令。 因此，第一计算机程序指令的执行允许对存储器层次的控制，这进而使得用户对存储器层级进行控制。

公开(公告)号：US06721944B2

公开(公告)日：2004-04-13

申请号：US09761226

申请日：2001-01-16

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F945

CPC分类号： G06F9/3851 ,  G06F9/3842

摘要： One embodiment of the present invention provides a system that marks memory elements based upon how information retrieved from the memory elements affects speculative program execution. This system operates by allowing a programmer to examine source code that is to be compiled into executable code for a head thread that executes program instructions, and for a speculative thread that executes program instructions in advance of the head thread. During read operations to memory elements by the speculative thread, this executable code generally causes the speculative thread to update status information associated with the memory elements to indicate that the memory elements have been read by the speculative thread. Next, the system allows the programmer to identify a given read operation directed to a given memory element, wherein a given value retrieved from the given memory element during the given read operation does not affect subsequent execution of the speculative thread. The programmer is then allowed to insert a hint into the source code specifying that the speculative thread is not to update status information during the given read operation directed to the given memory element. Next, the system compiles the source code, including the hint, into the executable code, so that during the given read operation, the executable code does not cause the speculative thread to update status information associated with the given memory element to indicate that the given memory element has been read by the speculative thread.

摘要翻译： 本发明的一个实施例提供了一种基于如何从存储器元件检索的信息影响推测程序执行来标记存储器元件的系统。 该系统通过允许程序员检查要编译成用于执行程序指令的头部线程的可执行代码的源代码，以及在头部线程之前执行程序指令的推测线程。 在通过推测线程对存储器元件的读取操作期间，该可执行代码通常导致推测线程更新与存储器元件相关联的状态信息，以指示存储器元件已被推测性线程读取。 接下来，系统允许程序员识别针对给定存储器元件的给定读取操作，其中在给定读取操作期间从给定存储器元件检索的给定值不影响推测线程的后续执行。 然后，程序员可以在源代码中插入提示，指定在给定的给定内存元素的给定读操作期间，推测线程不更新状态信息。 接下来，系统将源代码（包括提示）编译到可执行代码中，使得在给定的读取操作期间，可执行代码不会导致推测线程更新与给定存储器元件相关联的状态信息，以指示给定的 内存元素已被推测线程读取。

公开(公告)号：US06704862B1

公开(公告)日：2004-03-09

申请号：US09591142

申请日：2000-06-09

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F938

CPC分类号： G06F9/3842 ,  G06F9/3861

摘要： One embodiment of the present invention provides a system that supports exception handling through use of a conditional trap instruction. The system supports a head thread that executes program instructions and a speculative thread that speculatively executes program instructions in advance of the head thread. During operation, the system uses the speculative thread to execute code, which includes an instruction that can cause an exception condition. After the instruction is executed, the system determines if the instruction caused the exception condition. If so, the system writes an exception condition indicator to a register. At some time in the future, the system executes a conditional trap instruction which examines a value in the register. If the value in the register is an exception condition indicator, the system executes a trap handling routine to handle the exception condition. Otherwise, the system proceeds with execution of the code. In one embodiment of the present invention, prior to executing the instruction, the system allows a compiler to optimize a program containing the instruction. This optimization process includes scheduling an exception testing instruction associated with the instruction to occupy a free instruction slot following the instruction. This exception testing instruction determines if the instruction causes the exception condition. In one embodiment of the present invention, the trap handling routine triggers a rollback operation to undo operations performed by the speculative thread.

摘要翻译： 本发明的一个实施例提供一种通过使用条件陷阱指令来支持异常处理的系统。 该系统支持执行程序指令的头线程和在头部线程之前推测性地执行程序指令的推测线程。 在运行期间，系统使用推测线程来执行代码，其中包含可能导致异常情况的指令。 执行指令后，系统确定指令是否引起异常情况。 如果是这样，系统会将一个异常状态指示器写入寄存器。 在将来的某个时间，系统执行条件陷阱指令，检查寄存器中的值。 如果寄存器中的值是异常条件指示符，系统将执行陷阱处理例程来处理异常情况。 否则，系统继续执行代码。 在本发明的一个实施例中，在执行指令之前，系统允许编译器优化包含该指令的程序。 该优化处理包括调度与指令相关联的异常测试指令，以占用指令之后的空闲指令槽。 该异常测试指令确定指令是否导致异常情况。 在本发明的一个实施例中，陷阱处理例程触发回滚操作以撤消由推测线程执行的操作。

公开(公告)号：US06430649B1

公开(公告)日：2002-08-06

申请号：US09327398

申请日：1999-06-07

申请人： Shailender Chaudhry ,  Marc Tremblay ,  James M. O'Connor

发明人： Shailender Chaudhry ,  Marc Tremblay ,  James M. O'Connor

IPC分类号： G06F938

CPC分类号： G06F9/3842 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that enforces dependencies between memory references within a load store unit (LSU) in a processor. When a write request is received in the load store unit, the write request is loaded into a store buffer in the LSU. The write request may include a “watch address” specifying that a subsequent load from the watch address cannot occur before the write request completes. Note that the watch address is not necessarily the same as the destination address of the write operation. When a read request is received in the load store unit, the read request is loaded into a load buffer of the LSU. The system determines if the read request is directed to the same address as a matching watch address in the store buffer. If so, the system waits for the write request associated with the matching watch address to complete before completing the read request. In one embodiment of the present invention, if the read request is directed to the same address as a matching write request in the store buffer, the system completes the read request by returning a data value contained in the matching write request without going out to memory. In one embodiment of the present invention, the system provides an executable code write instruction that specifies the watch address.

摘要翻译： 本发明的一个实施例提供了一种在处理器中的加载存储单元（LSU）内实现存储器引用之间的依赖性的系统。 当在加载存储单元中接收到写请求时，写请求被加载到LSU中的存储缓冲器中。 写请求可以包括指定来自监视地址的后续加载在写请求完成之前不会发生的“监视地址”。 请注意，手表地址不一定与写入操作的目标地址相同。 当在加载存储单元中接收到读请求时，读请求被加载到LSU的加载缓冲器中。 系统确定读请求是否与存储缓冲区中匹配的监视地址指向相同的地址。 如果是这样，则在完成读取请求之前，系统等待与匹配的监视地址相关联的写入请求完成。 在本发明的一个实施例中，如果读请求针对与存储缓冲器中的匹配写请求相同的地址，则系统通过返回包含在匹配写请求中的数据值来完成读请求，而不用外存 。 在本发明的一个实施例中，系统提供了一个指定监视地址的可执行代码写入指令。

公开(公告)号：US08898436B2

公开(公告)日：2014-11-25

申请号：US12426550

申请日：2009-04-20

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30098 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3838 ,  G06F9/384

摘要： A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

摘要翻译： 在处理器中的寄存器文件包括第一大小的n位的第一多个寄存器。 解码器使用将寄存器文件分成具有第二大小的第二多个寄存器M的映射。 具有第二大小的每个寄存器在连续的名称空间中被分配不同的名称。 第二大小的每个寄存器包括多个N个第一大小的寄存器，n位。 多个N个寄存器中的每个寄存器被分配与包括该多个寄存器的第二大小的寄存器相同的名称。 状态信息保存在每个n位寄存器的寄存器文件中。 通过连续名称空间检测指令对其他指令的依赖性。 状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。

公开(公告)号：US20120331314A1

公开(公告)日：2012-12-27

申请号：US13529761

申请日：2012-06-21

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC分类号： G06F1/32

CPC分类号： G06F9/3867 ,  G06F1/206 ,  G06F1/3203 ,  G06F9/3869 ,  Y02D10/16

摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不物理地改变处理器周期或任何处理器供电电压。

公开(公告)号：US07818510B2

公开(公告)日：2010-10-19

申请号：US11832777

申请日：2007-08-02

申请人： Marc Tremblay ,  Quinn A. Jacobson ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Quinn A. Jacobson ,  Shailender Chaudhry

IPC分类号： G06F12/14

CPC分类号： G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815

摘要： One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

摘要翻译： 本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。 如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。

公开(公告)号：US07711928B2

公开(公告)日：2010-05-04

申请号：US11082282

申请日：2005-03-16

申请人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

发明人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

IPC分类号： G06F9/30

CPC分类号： G06F9/30061 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842

摘要： A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.

摘要翻译： 为用户提供了通过软件对存储器层次结构进行抽样的方法。 这允许用户通过软件来增强内存级并行性。 响应于第一计算机程序指令的执行，读取执行第二计算机程序指令所需的信息的状态。 在状态为第一状态时，继续执行第二计算机程序指令。 或者，在状态是与第一状态不同的第二状态的情况下执行第三计算机程序指令。 因此，第一计算机程序指令的执行允许对存储器层次的控制，这进而使得用户对存储器层级进行控制。

公开(公告)号：US07484080B2

公开(公告)日：2009-01-27

申请号：US11103912

申请日：2005-04-11

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/00

CPC分类号： G06F9/3863 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3865

摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store. If the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters the scout mode, without waiting for the deferred queue to eventually fill.

摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行指令和后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中以程序顺序执行其他非延迟指令。 在执行提前模式期间遇到存储器时，系统确定存储缓冲区是否已满。 如果是这样，系统将预取商店的高速缓存线，并延迟商店的执行。 如果在执行超前模式期间遇到的存储的数量超过了存储缓冲区的容量，这意味着由于存储缓冲区被选通，在执行提前模式下，存储缓冲区将永远不会有额外的空间来接受附加存储， 系统直接进入侦察模式，无需等待延期队列最终填满。