公开(公告)号：US20080181081A1

公开(公告)日：2008-07-31

申请号：US11669829

申请日：2007-01-31

Applicant: PETER MAYER ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

Inventor： PETER MAYER ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

IPC: G11B7/00

CPC classification number: G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method and apparatus for accessing one or more memory devices using an optical multi-mode signal. The method includes providing an optical multi-mode signal including a first mode and a second mode and transmitting the optical multi-mode signal via an optical multi-mode bus to the one or more memory devices. The first mode is used to perform a first access to the one or more memory devices and the second mode is used to perform a second access to the one or more memory devices.

Abstract translation: 一种用于使用光学多模式信号访问一个或多个存储器件的方法和装置。 该方法包括提供包括第一模式和第二模式的光学多模式信号，并且经由光学多模式总线将光学多模式信号发送到一个或多个存储器件。 第一模式用于对一个或多个存储器设备执行第一次访问，并且第二模式用于对一个或多个存储器设备执行第二次访问。

公开(公告)号：US07398444B2

公开(公告)日：2008-07-08

申请号：US11220332

申请日：2005-09-06

Applicant: Martin Brox ,  Robert Kaiser ,  Volker Kilian ,  Wolfgang Spirkl

Inventor： Martin Brox ,  Robert Kaiser ,  Volker Kilian ,  Wolfgang Spirkl

IPC: G01R31/28

CPC classification number: G01R31/31725 ,  G01R31/31716 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50 ,  G11C29/50012

Abstract: The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.

Abstract translation: 本发明涉及一种用于测试存储器件的方法，该存储器件能够以正常操作模式和测试模式操作并且包含输出驱动器，输入驱动器和数据焊盘。 该方法包括以下步骤：将用于测试的测试输入数据传送到存储器件，使用测试输入数据执行测试，以便获得测试输出数据，读出的测试数据经由输出驱动器通过， 至少一个数据焊盘和输入驱动器，其中在测试期间切换输入驱动器和输出驱动器，使得能够同时从存储器件读取和写入数据，并且从 测试输出数据。 此外，本发明涉及用于测试存储器件的存储器件和系统。

公开(公告)号：US20080059687A1

公开(公告)日：2008-03-06

申请号：US11469338

申请日：2006-08-31

Applicant: Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

Inventor： Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

IPC: G06F13/00

CPC classification number: G06F13/4022 ,  G06F13/4239

Abstract: A method and system comprising at least two processing units that are connected with at least two memory units, wherein first data buses are connected with the memory units, wherein second data buses are connected with processing units, wherein cross bar switches are disposed between first and second data buses, and wherein a control unit controls the cross bar switches for connecting selected processing units with selected memory units.

Abstract translation: 一种方法和系统，包括至少两个与至少两个存储器单元连接的处理单元，其中第一数据总线与存储单元连接，其中第二数据总线与处理单元连接，其中交叉开关设置在第一和第 第二数据总线，并且其中控制单元控制横杆开关，用于连接所选择的存储单元所选择的处理单元。

公开(公告)号：US20080056051A1

公开(公告)日：2008-03-06

申请号：US11469294

申请日：2006-08-31

Applicant: Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

Inventor： Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

IPC: G11C5/14 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C5/06 ,  G11C5/147 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/4093

Abstract: Memory with at least two memory banks each having memory cells, a control circuit, and at least one bank mode register, wherein the bank mode register stores information about an operation mode of a memory bank, wherein the control circuit operates at least one of the memory banks according to the information of the mode register.

Abstract translation: 具有至少两个具有存储单元的存储体的存储器，控制电路和至少一个存储体模式寄存器，其中存储体模式寄存器存储关于存储器组的操作模式的信息，其中控制电路操作至少一个 记忆库根据模式寄存器的信息。

公开(公告)号：US07317657B2

公开(公告)日：2008-01-08

申请号：US11319754

申请日：2005-12-29

Applicant: Martin Brox ,  Helmut Fischer

Inventor： Martin Brox ,  Helmut Fischer

IPC: G11C8/00

CPC classification number: G11C11/4076 ,  G11C7/1045 ,  G11C7/22

Abstract: The invention relates to a semiconductor memory device, a system with a semiconductor memory device, and a method for operating a semiconductor memory device, comprising the steps of reading out a data value, in particular a CAS latency time data value (CL) stored in a memory; activating or deactivating a device provided on said semiconductor memory device in support of a high speed operation, as a function of the data value (CL) stored.

Abstract translation: 本发明涉及半导体存储器件，具有半导体存储器件的系统和用于操作半导体存储器件的方法，包括以下步骤：读出数据值，特别是存储在存储器中的CAS等待时间数据值（CL） 记忆 作为存储的数据值（CL）的函数，激活或去激活设置在所述半导体存储器件上的设备以支持高速操作。

公开(公告)号：US07203102B2

公开(公告)日：2007-04-10

申请号：US10974019

申请日：2004-10-27

Applicant: Martin Brox ,  Russell Houghton ,  Helmut Schneider ,  Sabine Kieser

Inventor： Martin Brox ,  Russell Houghton ,  Helmut Schneider ,  Sabine Kieser

IPC: G11C7/10

CPC classification number: G11C11/4076 ,  G11C7/22 ,  G11C11/4096 ,  G11C2207/002

Abstract: A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal. The invention also relates to a tri-state driver device for driving the control signal. Further, there is a method for operating a memory, in which the memory has a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal.

Abstract translation: 一种半导体存储器，具有适于存储数据值的至少一个存储单元，并且适于通过由控制信号控制的开关装置连接到数据线。 本发明还涉及用于驱动控制信号的三态驱动器装置。 此外，存在用于操作存储器的方法，其中存储器具有适于存储数据值的存储单元，并且适于通过由控制信号控制的开关装置连接到数据线。

公开(公告)号：US20050179478A1

公开(公告)日：2005-08-18

申请号：US11041878

申请日：2005-01-25

Applicant: Martin Brox ,  Patrick Heyne ,  Alessandro Minzoni ,  Rajashekhar Rao ,  Kazimierz Szczypinski

Inventor： Martin Brox ,  Patrick Heyne ,  Alessandro Minzoni ,  Rajashekhar Rao ,  Kazimierz Szczypinski

IPC: G06F1/10 ,  G11C7/22 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/135 ,  H03L7/081 ,  H03L7/06

CPC classification number: H03L7/0805 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/135 ,  H03K2005/00097 ,  H03L7/0812

Abstract: The invention involves a clock pulse synchronization process as well as a device (1, 101) to be used in the synchronization of clock pulses (CLK), containing a first delay apparatus (2a) with variably controllable delay period (tvar), in which a clock pulse (CLK) or a signal derived from it, has a variably controllable delay period (tvar) imposed on it and is then emitted as a delayed signal (FBA), characterized in that in addition to the first delay apparatus (2a) with variably controllable delay period (tvar), a second delay apparatus (2b) with variably controllable delay period (tvar) is provided.

Abstract translation: 本发明涉及一种时钟脉冲同步过程以及在时钟脉冲（CLK）的同步中使用的装置（1,101），其包含具有可变可控延迟周期（t）的第一延迟装置（2a） 其中时钟脉冲（CLK）或从其导出的信号具有施加在其上的可变可控延迟时段（t 0 var），然后作为延迟信号发射 （FBA），其特征在于，除了具有可变可控延迟周期（tOUT var）的第一延迟装置（2a）之外，具有可变可控延迟周期（t）的第二延迟装置（2b） _{var ）。}

公开(公告)号：US20050169088A1

公开(公告)日：2005-08-04

申请号：US11043949

申请日：2005-01-28

Applicant: Martin Brox

Inventor： Martin Brox

IPC: G11C5/02 ,  G11C5/14 ,  G11C11/34

CPC classification number: G11C5/145 ,  G11C5/025

Abstract: A voltage booster device for semi-conductor components The invention relates to a semi-conductor component (1), in particular a memory component, with at least one voltage booster, which makes available an appropriate boosted voltage (VPP, VLL), and which is installed in a corresponding voltage booster area (101a) of the semi-conductor component (1), whereby the voltage booster area (101a) essentially extends parallel to several devices (9a, 8a, 8c), which are to be provided with the boosted voltage (VPP, VLL), in particular essentially parallel to the lines, for instance word lines (12a, 13a, 13b, 13c) controlled by the devices (9a, 8a, 8c).

Abstract translation: 一种用于半导体部件的升压装置技术领域本发明涉及一种具有至少一个升压器的半导体部件（1），特别是存储器部件，其具有适当的升压电压（VPP，VLL），并且其中 安装在所述半导体部件（1）的对应的升压区域（101a）中，由此所述升压器区域（101a）基本上平行于若干器件（9a，8a，cc）延伸， 提供升压电压（VPP，VLL），特别是基本上平行于线路，例如由装置（9a，8a，...）控制的字线（12a，13a，13b，13c） C）。

公开(公告)号：US06310793B1

公开(公告)日：2001-10-30

申请号：US09663583

申请日：2000-09-18

Applicant: Martin Brox ,  Karl-Peter Pfefferl

Inventor： Martin Brox ,  Karl-Peter Pfefferl

IPC: G11C502

CPC classification number: G11C8/12 ,  G11C8/14

Abstract: The segmented word line architecture has two master word lines, to which sub-word lines are alternately allocated. Two memory banks can thus be alternately assigned to the sub-word lines.

Abstract translation: 分段字线架构具有两条主字线，子字线被交替分配。 因此，可以将两个存储体交替地分配给子字线。

公开(公告)号：US08918597B2

公开(公告)日：2014-12-23

申请号：US12201876

申请日：2008-08-29

Applicant: Martin Brox ,  Ronny Schneider

Inventor： Martin Brox ,  Ronny Schneider

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  H03M7/00 ,  H03M5/00 ,  H03K19/003 ,  H03K19/23 ,  G11C7/10 ,  G11C7/06 ,  G06F13/42

CPC classification number: G06F13/4239

Abstract: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.

Abstract translation: 集成电路包括存储器单元阵列和数字标志发生器电路，该数字标志发生器电路被配置为基于从存储器单元发送的数据字中包含的逻辑零比特数是否大于阈值来生成数据反转标志。 数字标志发生器电路包括包括第一多个二进制逻辑电路的第一数字级。 每个二进制逻辑电路被配置为接收数据字的子集。