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166 条记录 (耗时 0.028 秒)

    Stacked semiconductor memory device
    21.
    发明授权
    Stacked semiconductor memory device 有权
    堆叠半导体存储器件

    公开(公告)号：US07209376B2

    公开(公告)日：2007-04-24

    申请号：US11151213

    申请日：2005-06-14

    申请人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

    发明人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

    IPC分类号： G11C5/06

    CPC分类号： G11C5/04 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/00

    摘要： A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

    摘要翻译： 具有减少在数据传送期间需要充电和放电并因此降低功耗的互连电容的目的的三维半导体存储器件具有：多个存储单元阵列芯片，其中作为分区的子行 组合存储器并且被布置为对应于输入/输出位，堆叠在第一半导体芯片上; 以及用于连接存储单元阵列的芯片间互连，使得子组的相应输入/输出位相同，这些芯片间互连以与输入/输出位数相对应的数量提供并通过存储单元阵列芯片 在堆叠的方向。

    Integrated circuit capable of high speed operations
    23.
    发明申请
    Integrated circuit capable of high speed operations 审中-公开
    具有高速运行的集成电路

    公开(公告)号：US20050053180A1

    公开(公告)日：2005-03-10

    申请号：US10933406

    申请日：2004-09-03

    申请人： Koichi Nose ,  Masayuki Mizuno

    发明人： Koichi Nose ,  Masayuki Mizuno

    IPC分类号： G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03K5/15 ,  H03K17/00 ,  H04L7/00

    CPC分类号： G06F1/10

    摘要： A semiconductor integrated circuit is disclosed for enabling faster operations than a clock frequency using multi-phase clocks, A clock generator circuit generates multi-phase clocks comprised of a plural-phase clocks which are the same in clock frequency but different in phase from one another. A clock distributor distributes the multi-phase clocks generated by the clock generator circuit within the integrated circuit. A logic circuit operates at an operating frequency higher than the clock frequency in synchronization with the multi-phase clocks generated by the clock generator circuit and distributed by the clock distributor.

    摘要翻译： 公开了一种半导体集成电路，用于实现比使用多相时钟的时钟频率更快的操作。时钟发生器电路产生由时钟频率相同但相位不同的多相时钟组成的多相时钟 。 时钟分配器分配由集成电路内的时钟发生器电路产生的多相时钟。 与由时钟发生器电路产生的并由时钟分配器分配的多相时钟同步地，工作频率高于时钟频率的工作频率。

    Method of manufacturing ceramic substrate
    24.
    发明授权
    Method of manufacturing ceramic substrate 有权
    制造陶瓷基板的方法

    公开(公告)号：US06374733B1

    公开(公告)日：2002-04-23

    申请号：US09601776

    申请日：2000-09-25

    申请人： Masaaki Hayama ,  Noboru Mouri ,  Hayami Matsunaga ,  Masayuki Mizuno ,  Eiji Kawamoto ,  Yuji Yagi

    发明人： Masaaki Hayama ,  Noboru Mouri ,  Hayami Matsunaga ,  Masayuki Mizuno ,  Eiji Kawamoto ,  Yuji Yagi

    IPC分类号： B41M110

    CPC分类号： H05K3/4647 ,  H01L21/4867 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/207 ,  H05K3/4053 ,  H05K3/4061 ,  H05K3/4605 ,  H05K3/4667 ,  H05K2203/0113 ,  H05K2203/0139

    摘要： The present invention relates to a manufacturing method of a ceramic substrate used in various electronic appliances, and more particularly to a manufacturing method of a ceramic substrate forming a conductor pattern by intaglio printing. A conductive paste is supplied in the intaglio by using any one of screen mask, metal mask, or drawing device, and therefore the conductive paste can be supplied uniformly in desired positions only. The supplying amount of the conductive paste can be adjusted by repeating printing, so that an optimum amount can be set depending on the pattern. As a result, a fine wiring pattern of thick film can be easily formed, and a ceramic circuit board low in wiring resistance, high in wiring density, and high in dimensional precision of wiring pattern can be obtained.

    摘要翻译： 本发明涉及用于各种电子设备的陶瓷基板的制造方法，更具体地说，涉及通过凹版印刷形成导体图案的陶瓷基板的制造方法。 通过使用屏幕掩模，金属掩模或拉制装置中的任何一个，在凹版中提供导电膏，因此导电浆可以均匀地供给到期望的位置。 可以通过重复印刷来调整导电浆料的供给量，从而可以根据图案设定最佳量。 结果，可以容易地形成厚膜的精细布线图案，并且可以获得布线电阻低，布线密度高，布线图形尺寸精度高的陶瓷电路板。

    Variable delay circuit
    25.
    发明授权
    Variable delay circuit 失效
    可变延迟电路

    公开(公告)号：US06304124B1

    公开(公告)日：2001-10-16

    申请号：US09020574

    申请日：1998-01-29

    申请人： Masayuki Mizuno

    发明人： Masayuki Mizuno

    IPC分类号： H03H1126

    CPC分类号： H03K5/131 ,  H03K3/0315 ,  H03K2005/00065 ,  H03K2005/00071

    摘要： A variable delay section comprises a gate element and a plurality of (N) delay elements for delaying the signal change on the output of the gate element. A difference between a first delay provided by n-th delay section and a second delay provided by (n+1)th delay section is constant for any of n's between 1 and N−1. A plurality of variable delay sections are cascaded to form a frequency multiplier, with the output of the last stage variable delay section being fed-back to the input of the first stage variable delay section through a selector. The other input of the selector is connected to the input of the variable delay circuit to allow the internal signal to pass the variable delay sections for K times.

    摘要翻译： 可变延迟部分包括门元件和用于延迟栅极元件的输出上的信号变化的多个（N）个延迟元件。 由第n延迟部分提供的第一延迟与由第（n + 1）个延迟部分提供的第二延迟之间的差在1和N-1之间的n中的任何一个上是恒定的。 多个可变延迟部分级联以形成倍频器，最后级可变延迟部分的输出通过选择器反馈到第一级可变延迟部分的输入端。 选择器的另一个输入端连接到可变延迟电路的输入端，以允许内部信号通过可变延迟部分K次。

    Signal value representing method and system
    26.
    发明授权
    Signal value representing method and system 有权
    信号值表示方法和系统

    公开(公告)号：US06243033B1

    公开(公告)日：2001-06-05

    申请号：US09351322

    申请日：1999-07-12

    申请人： Masayuki Mizuno

    发明人： Masayuki Mizuno

    IPC分类号： H03M166

    CPC分类号： H03M1/68 ,  H03M1/745 ,  H03M1/822

    摘要： A signal value representing method in which both wide dynamic range and high precision can be realized in combination with a low power source voltage. M+1 signal lines are used of which, M signal lines are digital signal values and one signal line is an analog signal value. The range of the values represented by the analog signal value representing method is equated to the smallest value of the digital signal value representing method. The signal value is represented by the combination of a discretely changing wide dynamic range signal, represented by the digital signal value representing method employing M signal lines and a continuously variable high precision signal which is represented by the analog signal value representing method employing a sole signal line and which represents a signal level position within the interval of the discrete values.

    摘要翻译： 可以结合低电源电压实现宽动态范围和高精度的信号值表示方法。 使用M + 1个信号线，其中M个信号线是数字信号值，一个信号线是模拟信号值。 由模拟信号值表示方法表示的值的范围等于数字信号值表示方法的最小值。 信号值由离散变化的宽动态范围信号的组合表示，由使用M个信号线的数字信号值表示方法表示，并且由使用单一信号的模拟信号值表示方法表示的连续可变高精度信号 线，其表示离散值的间隔内的信号电平位置。

    High speed signal level converting circuit having a reduced consumed electric power
    27.
    发明授权
    High speed signal level converting circuit having a reduced consumed electric power 失效
    具有降低的消耗电力的高速信号电平转换电路

    公开(公告)号：US5789942A

    公开(公告)日：1998-08-04

    申请号：US711111

    申请日：1996-09-09

    申请人： Masayuki Mizuno

    发明人： Masayuki Mizuno

    IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K17/16

    CPC分类号： H03K19/0013 ,  H03K19/018521

    摘要： A level converting circuit includes a first power supply line of a high potential, a second power supply line of a low potential, a third power supply line of a potential lower than that of the first power supply line by some degree, and a first internal power supply line. The level converting circuit also includes an inverter circuit configured to output an output potential equal to that of the second power supply line when an input signal is equal to a potential of the third power supply line, and another output potential equal to that of the first power supply line when the input signal is equal to a potential of the second power supply line. Furthermore, the level converting circuit includes a switch circuit for supplying to the first internal power supply line the potential of the third power supply line when the input signal is equal to a potential of the third power supply line, and the potential of the first power supply line when the input signal is equal to the potential of the second power supply line.

    摘要翻译： 电平转换电路包括高电位的第一电源线，低电位的第二电源线，一定程度上比第一电源线的电位低的第三电源线，以及第一内部 电源线。 电平转换电路还包括反相器电路，其被配置为当输入信号等于第三电源线的电位时，输出与第二电源线的输出电位相等的输出电位，另一个输出电位等于第一电源线的输出电位 当输入信号等于第二电源线的电位时，电源线。 此外，电平转换电路包括开关电路，用于当输入信号等于第三电源线的电位时，向第一内部电源线提供第三电源线的电位，并且第一电力的电位 当输入信号等于第二电源线的电位时，电源线。

    Distributed processing device for a digital filter
    28.
    发明授权
    Distributed processing device for a digital filter 失效
    用于数字滤波器的分布式处理装置

    公开(公告)号：US5524028A

    公开(公告)日：1996-06-04

    申请号：US116271

    申请日：1993-09-03

    申请人： Hiroaki Terada ,  Makoto Iwata ,  Masayuki Mizuno

    发明人： Hiroaki Terada ,  Makoto Iwata ,  Masayuki Mizuno

    IPC分类号： H03H17/00 ,  G06F17/00 ,  H03H17/02 ,  H04N1/40 ,  H03H7/30 ,  H04B1/10

    CPC分类号： H03H17/0241

    摘要： A horizontal synchronizing signal is counted by a binary counter. A first switch is switched in response to the count value, whereby signal data is classified. A sampling clock signal is counted by a binary counter. An output of the first switch is switched by second and third switches in response to the count value, whereby the data input rate of signal data is reduced. Each classified signal is subjected to filtering by a two-dimensional FIR digital filter.

    摘要翻译： 水平同步信号由二进制计数器计数。 响应于计数值切换第一开关，从而信号数据被分类。 采样时钟信号由二进制计数器计数。 响应于计数值，由第二和第三开关切换第一开关的输出，从而降低信号数据的数据输入速率。 每个分类的信号通过二维FIR数字滤波器进行滤波。

    Motor start examining device and method
    29.
    发明授权
    Motor start examining device and method 失效
    电机启动检查装置和方法

    公开(公告)号：US5445017A

    公开(公告)日：1995-08-29

    申请号：US289228

    申请日：1994-08-12

    申请人： Masayuki Mizuno

    发明人： Masayuki Mizuno

    IPC分类号： G02B26/12 ,  H02P1/04 ,  H04N1/053 ,  H04N1/113 ,  G01N15/00

    CPC分类号： H04N1/0476 ,  G02B26/122 ,  H02P1/04 ,  H04N1/053 ,  H04N1/1135 ,  H04N2201/0471 ,  H04N2201/04755 ,  Y10S388/921

    摘要： The present invention is suitable for examination of the rotating state of a Polygonal mirror motor in an image forming apparatus. It is judged whether or not the rotational speed of the motor is a target speed until a first time period has elapsed since the supply of power to the motor for rotating a Polygonal mirror was started every other second time period sufficiently shorter than the first time period and continuously checked over a third time period which is sufficiently shorter than the second time period. If it is judged that the rotational speed of the motor is the target speed continuously for the third time period, it is judged again whether or not the rotational speed of the motor is the target speed after an elapse of a fourth time period since the judgment. If the rotational speed of the motor is the target speed, the motor outputs a signal indicating that the motor is stabilized at the target speed. If the rotational speed of the motor is not the target speed, the motor further waits until a fifth time period has elapsed for judging whether or not the rotational speed of the motor is the target speed. If the rotational speed of the motor is the target speed, the motor outputs a signal indicating that the motor is stabilized at the target speed. Image formation processing is performed in response to the signal indicating that the motor is stabilized at the target speed.

    摘要翻译： 本发明适用于图像形成装置中的多角镜电机的旋转状态的检查。 在从第一时间段到第一时间段之后，判断电动机的转速是否为从第一时间段到第一时间段以后的时间长度，每隔一个时间间隔开始， 并且连续检查比第二时间段足够短的第三时间段。 如果判断为电动机的转速是第三时间段连续的目标速度，则再次判断电动机的转速是否是从判定起经过第四时间段之后的目标速度 。 如果电动机的转速是目标转速，则电动机输出指示电动机稳定在目标速度的信号。 如果电动机的转速不是目标速度，则电动机进一步等待直到第五时间段，以判断电动机的转速是否为目标速度。 如果电动机的转速是目标转速，则电动机输出指示电动机稳定在目标速度的信号。 响应于指示电动机稳定在目标速度的信号执行图像形成处理。