公开(公告)号：US07510904B2

公开(公告)日：2009-03-31

申请号：US11556739

申请日：2006-11-06

申请人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

发明人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

IPC分类号： H01L21/00

CPC分类号： H01L31/101

摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

摘要翻译： 本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。 该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。 该器件通过利用掩埋绝缘层，通过利用Ge吸收层，利用薄的吸收层和窄电极间隔的低电压操作以及兼容性来兼容宽泛的光谱，利用埋入的绝缘层来隔离底层衬底中产生的载流子， 通过其平面结构和使用IV族吸收材料的CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。 该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

公开(公告)号：US07485537B2

公开(公告)日：2009-02-03

申请号：US11490326

申请日：2006-07-20

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/76

CPC分类号： H01L29/7317 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66265

摘要： The present invention provides a a method of fabricating bipolar junction transistors (BJTs) on selected areas of a very thin buried oxide (BOX) using a conventional silicon-on-insulator (SOI) starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种使用具有厚BOX的常规绝缘体上硅（SOI）起始晶片在非常薄的掩埋氧化物（BOX）的选定区域上制造双极结型晶体管（BJT）的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US20080258180A1

公开(公告)日：2008-10-23

申请号：US11306721

申请日：2006-01-09

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Qiqing Ouyang ,  Siddhartha Panda

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Qiqing Ouyang ,  Siddhartha Panda

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.

摘要翻译： 半导体结构和制造半导体结构的方法包括具有横截面沙漏形沟道区域的半导体衬底。 应力施加层位于沟道区附近。 沙漏形状可以在通过应力施加层纵向压缩应力时提供通道区域内的增强的垂直拉伸应力。

公开(公告)号：US20080042202A1

公开(公告)日：2008-02-21

申请号：US11874753

申请日：2007-10-18

申请人： Meikei Ieong ,  Thomas Ludwig ,  Edward Nowak ,  Qiqing Ouyang

发明人： Meikei Ieong ,  Thomas Ludwig ,  Edward Nowak ,  Qiqing Ouyang

IPC分类号： H01L27/12

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66818 ,  H01L29/785

摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.

摘要翻译： 提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。 本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。 本发明还涉及利用本发明的方法形成的所得半导体结构。

公开(公告)号：US20060263993A1

公开(公告)日：2006-11-23

申请号：US11490326

申请日：2006-07-20

申请人： Herbert Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul Papworth ,  Christopher Sheraw ,  Michael Steigerwalt

发明人： Herbert Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul Papworth ,  Christopher Sheraw ,  Michael Steigerwalt

IPC分类号： H01L21/331

CPC分类号： H01L29/7317 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66265

摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

公开(公告)号：US20060234481A1

公开(公告)日：2006-10-19

申请号：US11209408

申请日：2005-08-23

申请人： Jack Chu ,  Steven Koester ,  Qiqing Ouyang

发明人： Jack Chu ,  Steven Koester ,  Qiqing Ouyang

IPC分类号： H01L21/425

CPC分类号： H01L29/66431 ,  H01L29/7782 ,  Y10S438/933 ,  Y10S438/938

摘要： A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping to be formed using a standard technique such as ion implantation, and further allows the high-mobility channel to be in close proximity to the counter doping without degradation of the mobility.

摘要翻译： 制造高迁移率半导体层结构的结构和方法以及包括高迁移率导电沟道的场效应晶体管（MODFET），同时保持反掺杂以控制有害的短沟道效应。 MODFET设计包括高迁移率导电沟道层，其中该方法允许使用诸如离子注入的标准技术形成反相掺杂，并且还允许高迁移率通道紧邻反掺杂而不降解 流动性。

公开(公告)号：US20060163631A1

公开(公告)日：2006-07-27

申请号：US10622477

申请日：2003-07-18

申请人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

发明人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10864

摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

摘要翻译： 在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。 晶体管栅极被设计代替通道。 用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。 存储节点附近的栅极材料为n型掺杂多晶硅。 位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。 该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

公开(公告)号：US20050285187A1

公开(公告)日：2005-12-29

申请号：US10930404

申请日：2004-08-31

申请人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

发明人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

IPC分类号： H01L29/10 ,  H01L29/165 ,  H01L29/24 ,  H01L29/76

CPC分类号： H01L29/165 ,  H01L29/1054 ,  H01L29/24 ,  H01L29/7842 ,  H01L29/7843

摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

摘要翻译： 本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。 单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。 单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。 单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。 本发明还提供了用应变诱导隔离区增加双轴应变的方法。 本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

公开(公告)号：US20050045905A1

公开(公告)日：2005-03-03

申请号：US10652400

申请日：2003-08-29

申请人： Jack Chu ,  Qiqing Ouyang

发明人： Jack Chu ,  Qiqing Ouyang

IPC分类号： H01L21/335 ,  H01L29/10 ,  H01L29/778 ,  H01L29/786 ,  H01L29/24

CPC分类号： H01L29/1054 ,  H01L29/78687

摘要： A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.

摘要翻译： 基于硅和硅锗的半导体MODFET器件的设计与制造方法。 MODFET设计包括高移动性层结构，能够实现超高速，低噪声，适用于各种通信应用，包括射频，微波，亚毫米波和毫米波。 外延场效应晶体管层结构包括用于高迁移率应变n沟道和p沟道晶体管的关键（垂直和横向）器件缩放和层结构设计，其包含硅和硅锗层，以在超超导体上形成最佳调制掺杂异质结构 薄的SOI或SGOI衬底，能够实现大大提高射频性能。

公开(公告)号：US07915653B2

公开(公告)日：2011-03-29

申请号：US11556755

申请日：2006-11-06

申请人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

发明人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

IPC分类号： H01L27/146

CPC分类号： H01L31/101

摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

摘要翻译： 本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。 该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。 该器件通过利用掩埋绝缘层，通过利用Ge吸收层，利用薄吸收层和窄电极间隔的低电压操作以及兼容性来兼容通过利用掩埋绝缘层来隔离在下面的衬底中产生的载流子，在广谱上的高量子效率， 通过其平面结构和使用IV族吸收材料的CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。 该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。