公开(公告)号：US20070247924A1

公开(公告)日：2007-10-25

申请号：US11399158

申请日：2006-04-06

申请人： Wei Zheng ,  Meng Ding

发明人： Wei Zheng ,  Meng Ding

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/14 ,  G11C16/0458 ,  G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

摘要： A memory includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory are provided in which electrons are Fowler-Nordheim (FN) tunneled out of at least one of the charge storage regions into a substrate to erase the at least one charge storage region of the memory. Other techniques are provided for programming a single charge storage region at multiple different levels or states.

摘要翻译： 存储器包括通过隔离区域与第二电荷存储区域间隔开的第一电荷存储区域。 提供了用于擦除存储器的技术，其中电子是Fowler-Nordheim（FN）从电荷存储区域中的至少一个隧道化到衬底中以擦除存储器的至少一个电荷存储区域。 提供了用于在多个不同级别或状态下编程单个电荷存储区域的其它技术。

公开(公告)号：US20070247923A1

公开(公告)日：2007-10-25

申请号：US11399130

申请日：2006-04-05

申请人： Meng Ding ,  Zhizheng Liu ,  Wei Zheng

发明人： Meng Ding ,  Zhizheng Liu ,  Wei Zheng

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： A dual-bit memory device includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions to erase the charge storage regions. Other techniques for programming a memory can be provided in which holes can be injected into at least one of the charge storage regions to program the charge storage regions.

摘要翻译： 双位存储器件包括通过隔离区域与第二电荷存储区域间隔开的第一电荷存储区域。 可以提供用于擦除存储器的技术，其中电子可以被注入到电荷存储区域中以擦除电荷存储区域。 可以提供用于编程存储器的其它技术，其中可以将空穴注入到至少一个电荷存储区域中以对电荷存储区域进行编程。

公开(公告)号：US07573103B1

公开(公告)日：2009-08-11

申请号：US11855704

申请日：2007-09-14

申请人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

发明人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

IPC分类号： H01L27/06

CPC分类号： H01L27/0266 ,  H01L27/0255

摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.

摘要翻译： 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN二极管包括连接到地的p型衬底，在p型衬底中形成的与p型衬底直接物理接触的n型材料的阱，并通过第一金属电连接到p型衬底 线，在n型材料的第一阱中形成的p型材料的阱，形成在p型材料的阱中的第一n型区，与p型材料的阱直接物理接触并连接到 存储器件的字线和形成在n型材料的阱中的与n型材料的阱直接物理接触并且经由第二p型材料电连接到p型材料的阱的第一p型区域 金属线。 PNP二极管包括连接到地的n型衬底，形成在n型衬底中的p型材料的阱与n型衬底直接物理接触并且经由第一金属电连接到n型衬底 线，在p型材料的第一阱中形成的n型材料的阱，形成在n型材料的阱中的与n型材料的阱直接物理接触的第一p型区，并连接到 存储器件的字线和形成在p型材料的阱中的第一n型区域，其与p型材料的阱直接物理接触并且经由第二类型的n型材料电连接到n型材料的阱 金属线。

公开(公告)号：US07463525B2

公开(公告)日：2008-12-09

申请号：US11615280

申请日：2006-12-22

申请人： Wei Zheng ,  Meng Ding ,  Sung-Chul Lee

发明人： Wei Zheng ,  Meng Ding ,  Sung-Chul Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C11/5642 ,  G11C16/0491 ,  G11C16/3454 ,  G11C16/349

摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.

摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，选择目标存储单元，并在其字线和位线上建立适当的编程电压。 阵列中未选择的字线偏置有轻微的负偏置电压，以减少或消除否则可能通过存储器单元传导的泄漏位线电流。 在验证操作（程序验证，软程序验证，擦除验证）和读取操作期间，也可以向未选择的单元施加轻微的负字线偏置电压，以减少或消除可能在验证和读取操作中引入错误的泄漏电流。

公开(公告)号：US20080151634A1

公开(公告)日：2008-06-26

申请号：US11615280

申请日：2006-12-22

申请人： Wei Zheng ,  Meng Ding ,  Sung-Chul Lee

发明人： Wei Zheng ,  Meng Ding ,  Sung-Chul Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5642 ,  G11C16/0491 ,  G11C16/3454 ,  G11C16/349

摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.

摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，选择目标存储单元，并在其字线和位线上建立适当的编程电压。 阵列中未选择的字线偏置有轻微的负偏置电压，以减少或消除否则可能通过存储器单元传导的泄漏位线电流。 在验证操作（程序验证，软程序验证，擦除验证）和读取操作期间，也可以向未选择的单元施加轻微的负字线偏置电压，以减少或消除可能在验证和读取操作中引入错误的泄漏电流。

公开(公告)号：US08031528B2

公开(公告)日：2011-10-04

申请号：US12557721

申请日：2009-09-11

申请人： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

发明人： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

公开(公告)号：US07345853B2

公开(公告)日：2008-03-18

申请号：US11745787

申请日：2007-05-08

申请人： Meng Ding ,  Surya Narayan Pattanaik ,  Chie Ching Poon ,  Neil Leslie Robertson

发明人： Meng Ding ,  Surya Narayan Pattanaik ,  Chie Ching Poon ,  Neil Leslie Robertson

IPC分类号： G11B5/39

CPC分类号： G11B5/11 ,  B23K1/0056 ,  B23K1/018 ,  B23K26/0622 ,  B23K26/354 ,  B23K2101/42 ,  G11B5/3906 ,  G11B5/40

摘要： A device according to one embodiment includes an electronic component such as an MR sensor, a pair of leads operatively coupled to the electronic component, and shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed. A magnetic storage system according to another embodiment includes magnetic media; and at least one head for reading from and writing to the magnetic media, each head having: a sensor; and a writer coupled to the sensor. The system also includes a pair of pads or leads operatively coupled to the head; shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed; a slider for supporting the head; and a control unit coupled to the head for controlling operation of the head.

摘要翻译： 根据一个实施例的装置包括诸如MR传感器的电子部件，可操作地耦合到电子部件的一对引线以及引线之间的短路材料，通过激光沉积工艺施加了短路材料，所述短路材料具有 被切断 根据另一实施例的磁存储系统包括磁介质; 以及用于从磁介质读取和写入至少一个头部，每个头部具有：传感器; 以及耦合到传感器的写入器。 该系统还包括可操作地耦合到头部的一对垫或引线; 在引线之间短路材料，通过激光沉积工艺施加的短路材料，短路材料已被切断; 用于支撑头部的滑块; 以及耦合到头部用于控制头部的操作的控制单元。

公开(公告)号：US07199986B2

公开(公告)日：2007-04-03

申请号：US10782301

申请日：2004-02-18

申请人： Marie-Claire Cyrille ,  Meng Ding ,  Kuok-San Ho ,  Prakash Kasiraj ,  Ernesto Marinero ,  James Lamar Nix ,  Brian York

发明人： Marie-Claire Cyrille ,  Meng Ding ,  Kuok-San Ho ,  Prakash Kasiraj ,  Ernesto Marinero ,  James Lamar Nix ,  Brian York

IPC分类号： G11B5/33

CPC分类号： G11B5/3932

摘要： A magnetic sensor is provided, having two bias layers separated by a decoupling layer to eliminate exchange coupling between the bias layers. The two bias layers may have differing coercivities, such that the biases provided by the bias layers to the free layer are independently adjustable. The grain structures of the two bias layers may be substantially decorrelated by the decoupling layer.

摘要翻译： 提供了一种磁传感器，其具有由解耦层隔开的两个偏置层，以消除偏置层之间的交换耦合。 两个偏置层可以具有不同的矫顽力，使得由偏置层提供给自由层的偏压是独立可调的。 两个偏置层的晶粒结构可以通过去耦层基本上去相关。

公开(公告)号：US20050241138A1

公开(公告)日：2005-11-03

申请号：US10835807

申请日：2004-04-30

申请人： Frederick Dill ,  Meng Ding ,  Kuok Ho ,  Jordan Katine ,  Scott MacDonald ,  Huey-Ming Tzeng

发明人： Frederick Dill ,  Meng Ding ,  Kuok Ho ,  Jordan Katine ,  Scott MacDonald ,  Huey-Ming Tzeng

IPC分类号： G11B5/187 ,  G11B5/31 ,  G11B5/39 ,  G11B5/40

CPC分类号： G11B5/3906 ,  G11B5/3163 ,  G11B5/40 ,  Y10T29/49021 ,  Y10T29/49043 ,  Y10T29/49048

摘要： A method of making a read sensor while protecting it from electrostatic discharge (ESD) damage involves forming a severable shunt during the formation of the read sensor. The method may include forming a resist layer over a plurality of read sensor layers; performing lithography with use of a mask to form the resist layer into a patterned resist which exposes left and right side regions over the read sensor layers as well as a shunt region; etching, with the patterned resist in place, to remove materials in the left and right side regions and in the shunt region; and depositing, with the patterned resist in place, left and right hard bias and lead layers in the left and right side regions, respectively, and in the shunt region for forming a severable shunt which electrically couples the left and right hard bias and lead layers together for ESD protection.

摘要翻译： 制造读取传感器同时防止静电放电（ESD）损坏的方法包括在形成读取的传感器期间形成可分离的分流。 该方法可以包括在多个读取传感器层上形成抗蚀剂层; 使用掩模执行光刻以将抗蚀剂层形成图案化的抗蚀剂，其在读取的传感器层以及分流区域上暴露左侧区域和右侧区域; 蚀刻，图案化抗蚀剂就位，以去除左右侧区域和分流区域中的材料; 并且分别在左侧区域和右侧区域以及分流区域中分别将图案化的抗蚀剂沉积在左侧和右侧的硬偏压和引线层，以形成可分离的分流器，其将左右硬偏压和引线层电耦合 一起为ESD保护。

公开(公告)号：US20080079061A1

公开(公告)日：2008-04-03

申请号：US11529166

申请日：2006-09-28

申请人： Meng Ding ,  Amol Joshi ,  Takashi Orimoto ,  Jayendra Bhakta ,  Lei Xue ,  Satoshi Torii ,  Robert Bertram Ogle

发明人： Meng Ding ,  Amol Joshi ,  Takashi Orimoto ,  Jayendra Bhakta ,  Lei Xue ,  Satoshi Torii ,  Robert Bertram Ogle

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L29/40117 ,  H01L29/4234

摘要： According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate dielectric stack includes a bottom oxide layer, a silicon-rich nitride layer situated on the bottom oxide layer, a low silicon-rich nitride layer situated on the silicon-rich nitride layer, and a top oxide layer situated on the low silicon-rich nitride layer. This embodiment results in a nitride based flash memory cell having improved program speed and retention while maintaining a high erase speed. In another embodiment, a flash memory cell may further comprise a high-K dielectric layer situated on the transistor gate dielectric stack.

摘要翻译： 根据一个示例性实施例，诸如闪存单元的结构包括位于半导体衬底上的晶体管栅极电介质堆叠。 晶体管栅极电介质堆叠包括底部氧化物层，位于底部氧化物层上的富含硅的氮化物层，位于富硅氮化物层上的低富硅氮化物层和位于低硅上的顶部氧化物层 富含氮化物层。 该实施例导致基于氮化物的闪存单元具有改善的编程速度和保持，同时保持高的擦除速度。 在另一个实施例中，快闪存储器单元还可以包括位于晶体管栅极电介质叠层上的高K电介质层。