中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

168 records (took 0.018 seconds)

    Managed NVM adaptive cache management
    24.
    发明授权
    Managed NVM adaptive cache management 有权

    公开(公告)号：US10572388B2

    公开(公告)日：2020-02-25

    申请号：US15691147

    申请日：2017-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen ,  Jianmin Huang ,  Sebastien Andre Jean ,  Kulachet Tanpairoj

    IPC: G06F12/08 ,  G06F12/02 ,  G06F3/06 ,  G06F12/0893

    Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

    VIRTUAL INDEXING IN A MEMORY DEVICE
    25.
    发明申请
    VIRTUAL INDEXING IN A MEMORY DEVICE 有权

    公开(公告)号：US20250156316A1

    公开(公告)日：2025-05-15

    申请号：US19022410

    申请日：2025-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

    IPC: G06F12/02

    Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

    SELECTIVELY ENABLING VALLEY TRACK FOR READING DATA
    26.
    发明申请
    SELECTIVELY ENABLING VALLEY TRACK FOR READING DATA 有权

    公开(公告)号：US20240419332A1

    公开(公告)日：2024-12-19

    申请号：US18741219

    申请日：2024-06-12

    Applicant: Micron Technology, Inc.

    Inventor： Tomer Eliash ,  Jianmin Huang ,  Zhengang Chen

    IPC: G06F3/06

    Abstract: Aspects of the present disclosure configure a memory sub-system controller to read data from a first portion of a memory based on read levels previously established while reading a second portion of the memory. The controller receives a request to read data from a first portion of a set of memory components. The controller identifies a second portion of the set of memory components that has been programmed with data within a threshold period of time of programming the data in the first portion. The controller retrieves a set of read threshold levels that have been previously computed in association with reading the data from the second portion. The controller reads the data from the first portion using the set of read threshold levels that have been previously computed in association with reading the data from the second portion.

    READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
    28.
    发明公开
    READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING 审中-公开

    公开(公告)号：US20240168879A1

    公开(公告)日：2024-05-23

    申请号：US18386760

    申请日：2023-11-03

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

    IPC: G06F12/02

    CPC classification number: G06F12/0246

    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

    Source address memory managment
    30.
    发明授权
    Source address memory managment 有权

    公开(公告)号：US11928356B2

    公开(公告)日：2024-03-12

    申请号：US17555160

    申请日：2021-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu

    IPC: G06F3/00 ,  G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064

    Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.

Patent Agency Ranking