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公开(公告)号：US20190139606A1
公开(公告)日：2019-05-09
申请号：US16235497
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Adam Johnson
IPC: G11C13/00
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.
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公开(公告)号：US10157669B2
公开(公告)日：2018-12-18
申请号：US13855208
申请日：2013-04-02
Applicant: Micron Technology, Inc.
Inventor： Adam Johnson
Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
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公开(公告)号：US09613676B1
公开(公告)日：2017-04-04
申请号：US15197416
申请日：2016-06-29
Applicant: Micron Technology, Inc.
Inventor： Bei Wang , Alessandro Calderoni , Wayne Kinney , Adam Johnson , Durai Vishak Nirmal Ramaswamy
IPC: G11C11/22 , G11C11/56 , H01L27/11507 , G11C14/00 , H01L27/11502
CPC classification number: G11C11/2275 , G11C11/22 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/5657 , G11C14/00 , H01L27/11502 , H01L27/11507
Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.
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公开(公告)号：US20150179256A1
公开(公告)日：2015-06-25
申请号：US14137586
申请日：2013-12-20
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Adam Johnson
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/1655 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0026 , G11C13/0033 , G11C2213/79
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.
Abstract translation: 描述了存储器系统和存储器编程方法。 根据一种布置，存储器系统包括单独配置为具有多个不同存储器状态的多个存储器单元，与存储器单元耦合的多个位线，与位线耦合的存取电路，并被配置为施加多个程序信号 到位线以对不同存储器状态之间的存储器单元进行编程，控制器被配置为控制访问电路以向与存储器单元之一耦合的位线之一提供第一编程信号和第二编程信号，以对一个存储器 从所述存储器状态的第一存储器状态到所述存储器状态的第二存储器状态，其中所述第二编程信号与所述第一编程信号相比具有增加的电特性，并且所述选择电路被配置为耦合与所述存储器状态紧邻的另一位线 位于具有与一个位线的第二电压不同的第一电压的节点 将第一和第二程序信号提供给一个位线。
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公开(公告)号：US20140112052A1
公开(公告)日：2014-04-24
申请号：US13658519
申请日：2012-10-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jonathan Strand , Adam Johnson , Xiaonan Chen , D.V. Nirmal Ramaswamy
CPC classification number: G11C13/0069 , G11C13/00 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C29/08 , G11C29/50008 , G11C2013/0073 , G11C2029/0409 , G11C2029/5006
Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.
Abstract translation: 描述了存储器编程方法和存储器系统。 一个示例性存储器编程方法包括：首先将第一信号施加到存储器单元以尝试将存储器单元编程到期望状态，其中第一信号对应于期望状态，在第一次施加之后，确定存储器单元不能放置 在所需状态下，在确定之后，向存储单元施加第二信号，其中第二信号对应于与期望状态不同的另一状态，并且在第二次施加之后，第三信号施加到存储单元 将存储器单元编程到所需状态，其中第三信号对应于期望状态。 描述附加的方法和装置。
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Patent Agency Ranking
公开(公告)号：US10770143B2
公开(公告)日：2020-09-08
申请号：US16235497
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Adam Johnson
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.
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公开(公告)号：US10304531B2
公开(公告)日：2019-05-28
申请号：US15690744
申请日：2017-08-30
Applicant: Micron Technology, Inc.
Inventor： Jonathan Strand , Adam Johnson , Xiaonan Chen , Durai Vishak Nirmal Ramaswamy
Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.
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公开(公告)号：US20190139591A1
公开(公告)日：2019-05-09
申请号：US16184827
申请日：2018-11-08
Applicant: Micron Technology, Inc.
Inventor： Bei Wang , Alessandro Calderoni , Wayne Kinney , Adam Johnson , Durai Vishak Nirmal Ramaswamy
IPC: G11C11/22 , H01L27/11507 , G11C11/56 , G11C14/00
CPC classification number: G11C11/2275 , G11C11/22 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/5657 , G11C14/00 , H01L27/11502 , H01L27/11507
Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.
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公开(公告)号：US10176868B2
公开(公告)日：2019-01-08
申请号：US14137586
申请日：2013-12-20
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Adam Johnson
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.
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公开(公告)号：US10170183B1
公开(公告)日：2019-01-01
申请号：US16102959
申请日：2018-08-14
Applicant: Micron Technology, Inc.
Inventor： Adam Johnson
Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
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