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公开(公告)号：US20190074060A1
公开(公告)日：2019-03-07
申请号：US16176417
申请日：2018-10-31
Applicant: Micron Technology, Inc.
Inventor： Emiliano Faraoni , Scott E. Sills , Alessandro Calderoni , Adam Johnson
IPC: G11C13/00
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.
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公开(公告)号：US20180358095A1
公开(公告)日：2018-12-13
申请号：US16102959
申请日：2018-08-14
Applicant: Micron Technology, Inc.
Inventor： Adam Johnson
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C29/74 , G11C2013/005 , G11C2013/0088 , G11C2213/32 , G11C2213/79
Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
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公开(公告)号：US20180137908A1
公开(公告)日：2018-05-17
申请号：US15858831
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Bei Wang , Alessandro Calderoni , Wayne Kinney , Adam Johnson , Durai Vishak Nirmal Ramaswamy
CPC classification number: G11C11/2275 , G11C11/22 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/5657 , G11C14/00 , H01L27/11502 , H01L27/11507
Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.
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公开(公告)号：US20180122476A1
公开(公告)日：2018-05-03
申请号：US15857402
申请日：2017-12-28
Applicant: Micron Technology, Inc.
Inventor： Adam Johnson
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C29/74 , G11C2013/005 , G11C2013/0088 , G11C2213/32 , G11C2213/79
Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
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公开(公告)号：US20180122475A1
公开(公告)日：2018-05-03
申请号：US15857370
申请日：2017-12-28
Applicant: Micron Technology, Inc.
Inventor： Adam Johnson
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C29/74 , G11C2013/005 , G11C2013/0088 , G11C2213/32 , G11C2213/79
Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
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Patent Agency Ranking
公开(公告)号：US20170365339A1
公开(公告)日：2017-12-21
申请号：US15690744
申请日：2017-08-30
Applicant: Micron Technology, Inc.
Inventor： Jonathan Strand , Adam Johnson , Xiaonan Chen , Durai Vishak Nirmal Ramaswamy
CPC classification number: G11C13/0069 , G11C13/00 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C29/08 , G11C29/50008 , G11C2013/0073 , G11C2029/0409 , G11C2029/5006
Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.
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公开(公告)号：US20140293674A1
公开(公告)日：2014-10-02
申请号：US13855208
申请日：2013-04-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Adam Johnson
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C29/74 , G11C2013/005 , G11C2013/0088 , G11C2213/32 , G11C2213/79
Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
Abstract translation: 一些实施例包括存储和检索RRAM阵列的数据的方法。 该阵列被细分为多个存储器位，每个存储器位具有至少两个存储单元。 通过同时改变存储器位内的所有存储单元的电阻状态来编程存储器位。 通过确定存储器位内的所有存储单元的总和电流来读取存储器位。 一些实施例包括具有多个存储器单元的RRAM。 每个存储器单元通过位线/字线组合唯一地寻址。 存储器位包含耦合在一起的多个存储器单元，每个存储器位内的耦合存储单元彼此处于相同的电阻状态。
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公开(公告)号：US11817147B2
公开(公告)日：2023-11-14
申请号：US16998834
申请日：2020-08-20
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Adam Johnson
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0033 , G11C11/1655 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/79
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.
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公开(公告)号：US11024378B2
公开(公告)日：2021-06-01
申请号：US16176417
申请日：2018-10-31
Applicant: Micron Technology, Inc.
Inventor： Emiliano Faraoni , Scott E. Sills , Alessandro Calderoni , Adam Johnson
IPC: G11C13/00
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.
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公开(公告)号：US09773551B2
公开(公告)日：2017-09-26
申请号：US14987630
申请日：2016-01-04
Applicant: Micron Technology, Inc.
Inventor： Jonathan Strand , Adam Johnson , Xiaonan Chen , Durai Vishak Nirmal Ramaswamy
CPC classification number: G11C13/0069 , G11C13/00 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C29/08 , G11C29/50008 , G11C2013/0073 , G11C2029/0409 , G11C2029/5006
Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.
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