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    Memory cells having a number of conductive diffusion barrier materials and manufacturing methods
    22.
    发明授权
    Memory cells having a number of conductive diffusion barrier materials and manufacturing methods 有权

    公开(公告)号：US10290800B2

    公开(公告)日：2019-05-14

    申请号：US15635945

    申请日：2017-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Davide Colombo

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.

    APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME
    28.
    发明申请
    APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME 有权
    具有导电阻挡材料的电极的装置及其形成方法

    公开(公告)号：US20140239245A1

    公开(公告)日：2014-08-28

    申请号：US13776485

    申请日：2013-02-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Swapnil A. Lengade ,  John M. Meldrim ,  Andrea Gotti

    IPC: H01L45/00

    CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144

    Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

    Abstract translation: 公开了具有导电阻挡材料的相变存储单元电极的制造方法和制造方法。 在一个实例中，装置包括与第一硫族化物结构堆叠在一起的第一硫族化物结构和第二硫族化物结构。 第一电极部分耦合到第一硫族化物结构，并且第二电极部分耦合到第二硫族化物结构。 导电阻挡材料设置在第一和第二电极部分之间。

    Techniques for forming memory structures
    29.
    发明授权
    Techniques for forming memory structures 有权

    公开(公告)号：US11575085B2

    公开(公告)日：2023-02-07

    申请号：US17165549

    申请日：2021-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Gotti ,  Pavan Reddy K. Aella ,  Dale W. Collins

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

    Fabrication of electrodes for memory cells
    30.
    发明授权
    Fabrication of electrodes for memory cells 有权

    公开(公告)号：US11545623B2

    公开(公告)日：2023-01-03

    申请号：US17066409

    申请日：2020-10-08

    Applicant: Micron Technology, Inc.

    Inventor： Pengyuan Zheng ,  Yongjun J. Hu ,  Yao Jin ,  Hongqi Li ,  Andrea Gotti

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.

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