公开(公告)号：US11538822B2

公开(公告)日：2022-12-27

申请号：US16445065

申请日：2019-06-18

Applicant: Micron Technology, inc.

Inventor： John D. Hopkins ,  Justin D. Shepherdson ,  Collin Howder ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/285 ,  H01L27/11519 ,  H01L29/66 ,  H01L21/28

Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

公开(公告)号：US20220336485A1

公开(公告)日：2022-10-20

申请号：US17233158

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin D. Shepherdson ,  Chet E. Carter

IPC: H01L27/11578 ,  H01L27/11575 ,  H01L25/065

Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

公开(公告)号：US11411015B2

公开(公告)日：2022-08-09

申请号：US17151344

申请日：2021-01-18

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/3213

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.

公开(公告)号：US20220238548A1

公开(公告)日：2022-07-28

申请号：US17158888

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Litao Yang ,  Albert Fayrushin ,  Naveen Kaushik ,  Jian Li ,  Collin Howder

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses. Additional microelectronic devices, related methods, and electronic systems are also disclosed.

公开(公告)号：US20220231046A1

公开(公告)日：2022-07-21

申请号：US17714924

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L21/822

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11315877B2

公开(公告)日：2022-04-26

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20210143167A1

公开(公告)日：2021-05-13

申请号：US17151344

申请日：2021-01-18

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.

公开(公告)号：US20200168624A1

公开(公告)日：2020-05-28

申请号：US16203200

申请日：2018-11-28

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Rita J. Klein

IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

公开(公告)号：US20200066747A1

公开(公告)日：2020-02-27

申请号：US16111648

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Mark W. Kiehlbauch ,  Nancy M. Lomeli

IPC: H01L27/11582 ,  H01L29/66 ,  H01L21/28 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

公开(公告)号：US10553607B1

公开(公告)日：2020-02-04

申请号：US16111648

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Mark W. Kiehlbauch ,  Nancy M. Lomeli

IPC: H01L27/11 ,  H01L27/11582 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L21/027 ,  H01L21/28

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.