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    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS
    21.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20230005855A1

    公开(公告)日：2023-01-05

    申请号：US17364429

    申请日：2021-06-30

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  G11C11/408 ,  G11C11/4091

    Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry at least partially overlying the first semiconductive structure, first back-end-of-line (BEOL) structures over and in electrical communication with the control logic circuitry, and first isolation material covering the control logic circuitry and the first BEOL structures. A second microelectronic device structure is bonded over the first BEOL structures to form a first assembly. The first assembly is vertically inverted. A third microelectronic device structure comprising a second semiconductor structure is bonded over the vertically inverted first assembly to form a second assembly. Memory cells comprising portions of the second semiconductor structure are formed after forming the second assembly. Second BEOL structures are formed over the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.

    THIN FILM TRANSISTOR DECK SELECTION IN A MEMORY DEVICE
    22.
    发明申请
    THIN FILM TRANSISTOR DECK SELECTION IN A MEMORY DEVICE 有权

    公开(公告)号：US20220375951A1

    公开(公告)日：2022-11-24

    申请号：US17327031

    申请日：2021-05-21

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Vimercati ,  Fatma Arzum Simsek-Ege

    IPC: H01L27/11507 ,  H01L27/11514 ,  H01L27/11509 ,  G11C11/22

    Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

    MULTIPLEXOR FOR A SEMICONDUCTOR DEVICE
    23.
    发明申请
    MULTIPLEXOR FOR A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220285351A1

    公开(公告)日：2022-09-08

    申请号：US17190705

    申请日：2021-03-03

    Applicant: Micron Technology, Inc.

    Inventor： Yuan He ,  Fatma Arzum Simsek-Ege

    IPC: H01L27/108 ,  G11C11/4096 ,  G11C5/10 ,  G11C11/402 ,  H01L27/06 ,  G11C11/4091

    Abstract: A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

    INVENTORY MANAGEMENT
    24.
    发明申请
    INVENTORY MANAGEMENT 有权

    公开(公告)号：US20220058570A1

    公开(公告)日：2022-02-24

    申请号：US16997785

    申请日：2020-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Gitanjali T. Ghosh ,  Yixin Yan ,  Rosa M. Avila-Hernandez

    IPC: G06Q10/08 ,  G06N20/00

    Abstract: Methods, apparatuses, and systems associated with inventory management are described. Examples can include receiving at a processor first signaling from a first sensor device configured to monitor the interior of a first enclosure and receiving at the processor second signaling from a second sensor device configured to monitor the interior of a second enclosure. Examples can include writing from the processor to a storage device coupled to the processor data that is based at least in part on a combination of the first and second signaling, identifying a quantity or amount of at least one item in the first enclosure and at least one item in the second enclosure, and transmitting third signaling when the quantity or amount of the at least one item in the first enclosure or the at least one item in the second enclosure is less than a threshold value.

    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
    26.
    发明申请
    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells 审中-公开

    公开(公告)号：US20200258910A1

    公开(公告)日：2020-08-13

    申请号：US16861093

    申请日：2020-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/11556

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

    Integrated structures of vertically-stacked memory cells
    27.
    发明授权
    Integrated structures of vertically-stacked memory cells 审中-公开

    公开(公告)号：US10672785B2

    公开(公告)日：2020-06-02

    申请号：US14679926

    申请日：2015-04-06

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/1157

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

    Integrated structures and methods of forming vertically-stacked memory cells
    28.
    发明授权
    Integrated structures and methods of forming vertically-stacked memory cells 有权

    公开(公告)号：US10600807B2

    公开(公告)日：2020-03-24

    申请号：US16528454

    申请日：2019-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

    IPC: H01L21/02 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/115 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

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