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公开(公告)号：US08773187B2
公开(公告)日：2014-07-08
申请号：US13953500
申请日：2013-07-29
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
IPC: H03H11/26
CPC classification number: H03K5/133 , H03H11/26 , H03H11/265 , H03K5/131
Abstract: Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.
Abstract translation: 描述了模拟延迟线和模拟延迟系统（例如并入模拟延迟线的DLL）的示例，以及用于自适应偏置的电路和方法。 描述自适应偏置的实施例，并且可以在启动期间产生用于模拟延迟线的偏置信号。 偏置信号可以部分地基于模拟延迟线的操作频率。
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公开(公告)号：US20140070860A1
公开(公告)日：2014-03-13
申请号：US14083100
申请日：2013-11-18
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
IPC: H03K3/012
CPC classification number: H03K3/012 , H01L23/481 , H01L23/5226 , H01L25/0657 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H03K19/018507 , H03K19/018585 , H01L2924/00
Abstract: Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.
Abstract translation: 描述了包括对应于单个通孔的多个驱动器的装置和方法。 可以选择多个驱动器单独或一起操作，以通过单个通孔驱动信号。 描述附加的装置和方法。
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公开(公告)号：US20220021567A1
公开(公告)日：2022-01-20
申请号：US17381987
申请日：2021-07-21
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis , Feng Lin
Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
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公开(公告)号：US20210273831A1
公开(公告)日：2021-09-02
申请号：US17323967
申请日：2021-05-18
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.
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公开(公告)号：US10447512B2
公开(公告)日：2019-10-15
申请号：US15885536
申请日：2018-01-31
Applicant: Micron Technology, Inc.
Inventor： Feng Lin , Timothy M. Hollis
Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.
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Patent Agency Ranking
公开(公告)号：US20190296740A1
公开(公告)日：2019-09-26
申请号：US16154291
申请日：2018-10-08
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
IPC: H03K19/00 , G11C5/06 , G11C7/10 , G11C29/02 , H03K19/0185 , H03K19/0175
Abstract: Methods, systems, and devices for output impedance calibration for signaling are described. Techniques are provided herein to adjust impedance levels associated with data transmitted using signaling and related techniques. In some cases, the signaling may be multi-level signaling. Such signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data.
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公开(公告)号：US10411704B1
公开(公告)日：2019-09-10
申请号：US16154291
申请日：2018-10-08
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
IPC: H03K19/0175 , H03K19/00 , G11C7/10 , G11C5/06 , G11C29/02 , H03K19/0185
Abstract: Methods, systems, and devices for output impedance calibration for signaling are described. Techniques are provided herein to adjust impedance levels associated with data transmitted using signaling and related techniques. In some cases, the signaling may be multi-level signaling. Such signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data.
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公开(公告)号：US20190273640A1
公开(公告)日：2019-09-05
申请号：US16415512
申请日：2019-05-17
Applicant: Micron Technology, Inc.
Inventor： Feng Lin , Timothy M. Hollis
Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.
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公开(公告)号：US20190044766A1
公开(公告)日：2019-02-07
申请号：US15885536
申请日：2018-01-31
Applicant: Micron Technology, Inc.
Inventor： Feng Lin , Timothy M. Hollis
CPC classification number: H04L25/4917 , G11C7/1057 , G11C7/1063 , G11C7/1069 , G11C7/1084 , G11C7/1096 , G11C7/20 , H04L7/0037 , H04L25/03038 , H04L25/03343 , H04L2025/03363
Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.
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公开(公告)号：US20170352644A1
公开(公告)日：2017-12-07
申请号：US15174019
申请日：2016-06-06
Applicant: Micron Technology, Inc.
Inventor： Feng Lin , Yuanzhong Wan
IPC: H01L25/065 , G11C11/4076 , G11C11/4091
CPC classification number: H01L25/0657 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4091 , H01L2225/06541 , H01L2225/06565
Abstract: Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.
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