公开(公告)号：US11094668B2

公开(公告)日：2021-08-17

申请号：US16711849

申请日：2019-12-12

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498

Abstract: Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

公开(公告)号：US20240282733A1

公开(公告)日：2024-08-22

申请号：US18410769

申请日：2024-01-11

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee ,  Bong Woo Choi

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/10 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/10152 ,  H01L2224/11013 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81192 ,  H01L2224/81815

Abstract: Methods, apparatuses, and systems related to a device having a delamination reduction mechanism disposed between a solder resist layer and a contact pad of a substrate. The substrate may include a solder opening in the solder resist layer over the contact pad. The delamination reduction mechanism may have bonding strengths relative to the solder resist layer and the contact pad that are greater than a bonding strength associated with a direct contact between the solder resist layer and the contact pad.

公开(公告)号：US11810894B2

公开(公告)日：2023-11-07

申请号：US17401887

申请日：2021-08-13

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/78 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/11013 ,  H01L2224/11464 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8112 ,  H01L2224/81193 ,  H01L2224/92143 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

公开(公告)号：US11688706B2

公开(公告)日：2023-06-27

申请号：US17021364

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L23/3178 ,  H01L24/05 ,  H01L24/81 ,  H01L2021/60022 ,  H01L2224/13147 ,  H01L2224/81801

Abstract: Embossed solder masks for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a package substrate includes the solder mask with non-planar features along a surface of the solder mask such that the area of the surface is increased. The non-planar features may correspond to concave recesses formed on the surface of the solder mask. Physical dimensions (e.g., widths, depths) and/or areal densities of the non-planar features of the embossed solder masks may vary based on local areas of the package substrate exclusive of conductive bumps. The non-planar features may be formed by pressing a mold having convex features against the surface of the solder mask. The solder mask may be heated while pressing the mold against the surface of the solder mask. In some embodiments, the mold includes regions lacking the convex features.

公开(公告)号：US11682563B2

公开(公告)日：2023-06-20

申请号：US17850978

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee ,  Chih Hong Wang

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/8192

Abstract: Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

公开(公告)号：US20220328326A1

公开(公告)日：2022-10-13

申请号：US17850978

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee ,  Chih Hong Wang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

Abstract: Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

公开(公告)号：US20220108970A1

公开(公告)日：2022-04-07

申请号：US17552830

申请日：2021-12-16

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/00

Abstract: A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.

公开(公告)号：US11264349B2

公开(公告)日：2022-03-01

申请号：US16721477

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/00

Abstract: A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.

公开(公告)号：US20220059500A1

公开(公告)日：2022-02-24

申请号：US17001435

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jong Sik Paek ,  Jungbae Lee

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

公开(公告)号：US20210384159A1

公开(公告)日：2021-12-09

申请号：US16892084

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jungbae Lee

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56

Abstract: This patent application relates to microelectronic device packages with internal EMI shielding, methods of fabricating and related electronic systems. One or more microelectronic devices of a package including multiple microelectronic devices are EMI shielded, and one or more other microelectronic devices of the package are located outside the EMI shielding.