公开(公告)号：US20240222305A1

公开(公告)日：2024-07-04

申请号：US18166517

申请日：2023-02-09

Applicant: Industrial Technology Research Institute

Inventor： Yu-Wei HUANG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/24 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/16225 ,  H01L2224/16501 ,  H01L2224/24227 ,  H01L2224/73209 ,  H01L2924/1517

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a circuit layer, and a plurality of contacts electrically connecting the circuit layer to the carrier. Each contact includes a metal portion and an insulating portion. The insulating portion surrounds the metal portion. A gap is formed between the contacts.

公开(公告)号：US20170256472A1

公开(公告)日：2017-09-07

申请号：US15448018

申请日：2017-03-02

Applicant: Infineon Technologies AG

Inventor： Sook Woon CHAN ,  Chau Fatt CHIANG ,  Kok Yau CHUA ,  Soon Lock GOH ,  Swee Kah LEE ,  Joachim MAHLER ,  Mei Chin NG ,  Beng Keh SEE ,  Guan Choon Matthew Nelson TEE

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/552 ,  H01L21/56 ,  C23C18/16 ,  C09D5/00 ,  C09D201/00 ,  C23C18/34 ,  C23C18/18 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/3192 ,  C09D5/002 ,  C09D5/24 ,  C09D201/00 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/1637 ,  C23C18/166 ,  C23C18/1689 ,  C23C18/182 ,  C23C18/1831 ,  C23C18/1834 ,  C23C18/1837 ,  C23C18/1868 ,  C23C18/1879 ,  C23C18/1882 ,  C23C18/34 ,  H01L21/56 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16501 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.

公开(公告)号：US20170162535A1

公开(公告)日：2017-06-08

申请号：US14963037

申请日：2015-12-08

Applicant: Amkor Technology, Inc.

Inventor： Glenn Rinne

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/11422 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13624 ,  H01L2224/13647 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/16503 ,  H01L2224/16505 ,  H01L2224/16507 ,  H01L2224/8102 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01016 ,  H01L2924/01005

Abstract: A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.

公开(公告)号：US20170103945A1

公开(公告)日：2017-04-13

申请号：US15384966

申请日：2016-12-20

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Akane KOBAYASHI ,  Yoshito AKUTAGAWA

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  C09J7/02 ,  H01L23/00

CPC classification number: H01L23/49838 ,  C09J7/22 ,  C09J201/00 ,  C09J2203/326 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68386 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/16104 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/00 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01322 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2221/68304 ,  H01L21/56 ,  H01L2221/68381

Abstract: A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer disposed on a main surface of the support body, the adhesive layer including a peeling layer which contains a third resin which is decomposed by light irradiation and a protective layer which is disposed on the peeling layer and contains a fourth resin; and a laminate disposed on the adhesive layer, the laminate including a first resin layer, a second resin layer disposed on the first resin layer, and a wiring pattern disposed at least between the first resin layer and the second resin layer. Accordingly, the semiconductor chip and the wiring substrate which is the external connection member can be separately manufactured, thereby improving manufacturing efficiency of the semiconductor device.

公开(公告)号：US09620470B2

公开(公告)日：2017-04-11

申请号：US15050558

申请日：2016-02-23

Applicant: FUJITSU LIMITED

Inventor： Kozo Shimizu ,  Seiki Sakuyama ,  Toyoo Miyajima

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H05K3/34 ,  B23K35/24 ,  B23K35/26 ,  B23K35/00 ,  B23K35/02 ,  H05K3/24 ,  B23K101/40

CPC classification number: H01L24/13 ,  B23K35/004 ,  B23K35/007 ,  B23K35/0244 ,  B23K35/24 ,  B23K35/262 ,  B23K35/264 ,  B23K2101/40 ,  H01L21/76843 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/73204 ,  H01L2224/81075 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2924/0103 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3494 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/0105 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01024 ,  H01L2924/01032 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a barrier metal film on a surface of at least one of a first electrode of a wiring board and a second electrode of a semiconductor element, providing a connection terminal between the first and second electrodes, the connection terminal being made of solder containing tin, bismuth and zinc, and bonding the connection terminal to the barrier metal film by heating the connection terminal and maintaining the temperature of the connection terminal at a constant temperature not lower than a melting point of the solder for a certain period of time.

公开(公告)号：US20160338201A1

公开(公告)日：2016-11-17

申请号：US15225379

申请日：2016-08-01

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Shinya KIYONO ,  Toshitaka HAYASHI ,  Sho FUJITA

IPC: H05K1/18 ,  H05K1/09 ,  H01L23/00 ,  H05K3/32

CPC classification number: H05K1/181 ,  B22F1/0059 ,  B22F7/064 ,  B23K35/025 ,  B23K35/302 ,  H01B1/22 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13194 ,  H01L2224/13347 ,  H01L2224/13487 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29347 ,  H01L2224/2939 ,  H01L2224/29487 ,  H01L2224/81075 ,  H01L2224/81193 ,  H01L2224/81359 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8184 ,  H01L2224/83075 ,  H01L2224/8384 ,  H01L2924/12044 ,  H05K1/097 ,  H05K3/32 ,  H05K2201/0257 ,  H05K2201/10015 ,  H05K2203/1131 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0541 ,  H01L2924/01029 ,  H01L2924/01046

Abstract: An electronic component module formed with the use of a copper particle paste which can ensure that even the inner part of a joint material is sintered, where copper particles are excellent in oxidation resistance, and a joint part is provided with high joint reliability; and a method for manufacturing the module.

Abstract translation: 一种电子部件模块，其特征在于，使用能够确保铜粒子的耐氧化性优异的连接材料的内部甚至烧结的铜粒子糊，并且接合部具有高的接头可靠性; 以及该模块的制造方法。

公开(公告)号：US20150061115A1

公开(公告)日：2015-03-05

申请号：US14013597

申请日：2013-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-TSE CHEN ,  HSIU-JEN LIN ,  CHIH-WEI LIN ,  MING-DA CHENG ,  CHIH-HANG TUNG ,  CHUNG-SHI LIU

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L21/56 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/0558 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).

Abstract translation: 导电互连结构包括接触垫; 在第一端连接到接触垫的导电体; 以及位于所述导电体的第二端上的导电层。 导电体具有垂直于接触垫表面的纵向方向。 导电体在垂直于导电体的纵向方向的截面（平面A）上具有平均粒径（a）。 导电层在平面A上具有平均粒径（b）。导电体和导电层由相同的材料组成，平均晶粒尺寸（a）大于平均晶粒尺寸（b）。

公开(公告)号：US20130320529A1

公开(公告)日：2013-12-05

申请号：US13482414

申请日：2012-05-29

Applicant: Gregory M. Fritz ,  Eric P. Lewandowski

Inventor： Gregory M. Fritz ,  Eric P. Lewandowski

IPC: H01L23/498 ,  H01L21/30

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13179 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/1713 ,  H01L2224/17163 ,  H01L2224/7525 ,  H01L2224/75264 ,  H01L2224/81192 ,  H01L2224/81222 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/8146 ,  H01L2224/81466 ,  H01L2224/818 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/0541 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2224/81121 ,  H01L2924/00012 ,  H01L2224/757 ,  H01L2924/014 ,  H01L2224/05552

Abstract: An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process.

公开(公告)号：US08097958B2

公开(公告)日：2012-01-17

申请号：US12298464

申请日：2007-04-18

Applicant: Susumu Sawada ,  Seiichi Nakatani ,  Seiji Karashima ,  Takashi Kitae

Inventor： Susumu Sawada ,  Seiichi Nakatani ,  Seiji Karashima ,  Takashi Kitae

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/323 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16501 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/83886 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/361 ,  H05K3/363 ,  H05K2203/083 ,  H05K2203/087 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/29311 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing the connection terminals of the first plate body 101. The connection terminals of the first and second plate bodies are connection terminals formed as projections on the surfaces of the first and second plate bodies. A conductive substance 108 is accumulated to cover at least a part of each side face of the connection terminals opposed to each other of the first and second plate bodies, and the connection terminals thus opposed are connected to each other via the conductive substance. The package thus formed is ready for a high-pin-count, narrow-pitch configuration of a next-generation semiconductor chip, and exhibits excellent productivity and reliability. The present invention is advantageous for such a package, for a connection structure applicable to the production of the package, and for a method of producing the connection structure.

Abstract translation: 连接结构（封装10）具有第一板体101和第二板体; 在第一板体101中，形成具有多个连接端子102的布线图案，第二板体具有面对第一板体101的连接端子配置的至少两个连接端子（电极端子104）。连接 第一和第二板体的端子是在第一和第二板体的表面上形成为突起的连接端子。 聚集导电物质108以覆盖第一和第二板体彼此相对的连接端子的每个侧面的至少一部分，并且由此相对的连接端子经由导电物质彼此连接。 这样形成的封装准备好用于下一代半导体芯片的高引脚数，窄间距配置，并且表现出优异的生产率和可靠性。 本发明对于这种包装，对于适用于包装的生产的连接结构以及制造连接结构的方法是有利的。

公开(公告)号：US20070222072A1

公开(公告)日：2007-09-27

申请号：US11475400

申请日：2006-06-26

Applicant: Chia-Jung Chang ,  Kwun-Yao Ho ,  Moriss Kung

Inventor： Chia-Jung Chang ,  Kwun-Yao Ho ,  Moriss Kung

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A chip package including a chip, a package substrate, and a plurality of bumps is provided. The chip has a plurality of chip pads disposed on a surface of the chip. The package substrate has a plurality of first substrate pads, a plurality of second substrate pads, and a surface bonding layer. The first substrate pads and second substrate pads are disposed on a surface of the package substrate. The surface bonding layer is disposed on the first substrate pads and second substrate pads, and covers a part of each second substrate pad. The bumps are respectively disposed between the chip pads and the surface bonding layer. The chip is electrically connected to the package substrate through the bumps. Each first substrate pad is electrically connected to one of the bumps, and each second substrate pad is electrically connected to at least two of the bumps.

Abstract translation: 提供了包括芯片，封装基板和多个凸块的芯片封装。 芯片具有设置在芯片表面上的多个芯片焊盘。 封装衬底具有多个第一衬底焊盘，多个第二衬底焊盘和表面粘合层。 第一衬底焊盘和第二衬底焊盘设置在封装衬底的表面上。 表面接合层设置在第一基板焊盘和第二基板焊盘上，并且覆盖每个第二基板焊盘的一部分。 凸块分别设置在芯片焊盘和表面粘接层之间。 芯片通过凸块电连接到封装衬底。 每个第一衬底焊盘电连接到凸块之一，并且每个第二衬底焊盘电连接到至少两个凸块。