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公开(公告)号：US20250045156A1
公开(公告)日：2025-02-06
申请号：US18774652
申请日：2024-07-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Fan Zhou
IPC: G06F11/10
Abstract: A decoding operation is performed by receiving a command to read a correction matrix comprising multiple bit-values from memory of a decoder. The decoding operation also includes, responsive to receipt of the command, generating, using circuitry of a decoder, a predetermined correction matrix comprising a same bit-value. The decoding operation further includes providing the predetermined correction matrix to a decision engine to perform the decoding operation.
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公开(公告)号：US12218681B2
公开(公告)日：2025-02-04
申请号：US17949635
申请日：2022-09-21
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad
Abstract: A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
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公开(公告)号：US20250028595A1
公开(公告)日：2025-01-23
申请号：US18773151
申请日：2024-07-15
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad , Leonid Minz , Sivagnanam Parthasarathy
IPC: G06F11/10
Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.
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公开(公告)号：US20250022492A1
公开(公告)日：2025-01-16
申请号：US18766414
申请日：2024-07-08
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik
IPC: G11C5/14
Abstract: A method includes determining that a power event involving a memory sub-system has occurred. The method further including in response to the determination that the power event has occurred, generating signaling indicative of performance of an operation to provide power to a plurality of memory components of the memory sub-system, where the signaling indicative of performance includes a power control signal is applied to a first memory component at a first time, and is applied to a second memory component at a second time that is subsequent to the first memory component entering a steady state.
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公开(公告)号：US12189596B2
公开(公告)日：2025-01-07
申请号：US18532552
申请日：2023-12-07
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Brian Toronyi
Abstract: A hash corresponding to a bit string is generated. The hash corresponds to an address location in a data structure associated with the bit string. An index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. In response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. In response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.
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Patent Agency Ranking
公开(公告)号：US20240427974A1
公开(公告)日：2024-12-26
申请号：US18749348
申请日：2024-06-20
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik
IPC: G06F30/3308 , G06F30/333 , G06F119/06
Abstract: An example method for power emulation and estimation includes estimating a functional power consumption value associated with a memory system by determining: a scan-based power estimation, scan-based power measurement, a calibration factor from correlating the scan-based power estimation to the scan-based power measurement and a correlated functional power using the calibration factor. The calibration factor can be applied to a functional power estimation in order to achieve better accuracy.
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公开(公告)号：US12170124B2
公开(公告)日：2024-12-17
申请号：US17692262
申请日：2022-03-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.
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公开(公告)号：US20240354031A1
公开(公告)日：2024-10-24
申请号：US18630313
申请日：2024-04-09
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0625 , G06F3/0679
Abstract: A method includes reading, from a memory array, a first counter identifier (ID) based on a pointer corresponding to an address location in the memory array in which the first counter ID is stored. The method includes incrementing the pointer to correspond to an address location in the memory array in which a second counter ID is stored and reading, from the memory array the second counter ID based on the pointer corresponding to the address location in the memory array in which the second counter ID is stored.
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公开(公告)号：US12044711B2
公开(公告)日：2024-07-23
申请号：US17824479
申请日：2022-05-25
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
CPC classification number: G01R19/0038 , G11C7/222 , H03K5/14 , H03K3/037
Abstract: A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.
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公开(公告)号：US20230384353A1
公开(公告)日：2023-11-30
申请号：US17824479
申请日：2022-05-25
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
CPC classification number: G01R19/0038 , H03K5/14 , G11C7/222 , H03K3/037
Abstract: A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.
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