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公开(公告)号：US11527287B1
公开(公告)日：2022-12-13
申请号：US17332242
申请日：2021-05-27
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Nevil N. Gajera , Lingming Yang , John F. Schreck
Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.
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公开(公告)号：US20220302212A1
公开(公告)日：2022-09-22
申请号：US17833596
申请日：2022-06-06
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Karthik Sarpatwari , Fabio Pellizzer , Nevil N. Gajera , Lei Wei
IPC: H01L27/24 , H01L23/528 , H01L45/00 , H01L23/532
Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.
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23.发明申请公开(公告)号：US20250157533A1
公开(公告)日：2025-05-15
申请号：US18908821
申请日：2024-10-08
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Raghukiran Sreeramaneni , Nevil N. Gajera
Abstract: System-in-package (SiP) having functional high bandwidth memory (HBM) devices, and associated systems and methods are disclosed herein. In some embodiments, the functional HBM devices can include a controller die, one or more volatile memory dies, a flash memory die, and an HBM bus communicably coupled to each of the controller, volatile memory, and flash memory dies. The flash memory die can include one or more word lines that each have multiple programmable memory cells, as well as multiple bit lines. Each of the bit lines is coupled to a corresponding programmable memory cell from each of the one or more word lines. During operation, the controller die is configured to control the volatile memory dies and the flash memory die, through a shared bus therebetween, to implement one or more neural network computing operations within the functional HBM device.
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公开(公告)号：US20250118366A1
公开(公告)日：2025-04-10
申请号：US18984830
申请日：2024-12-17
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Nevil N. Gajera , Lingming Yang , John F. Schreck
Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.
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公开(公告)号：US20250061960A1
公开(公告)日：2025-02-20
申请号：US18786291
申请日：2024-07-26
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Raghukiran Sreeramaneni , Nevil N. Gajera
Abstract: A stacked memory device (e.g., a high-bandwidth memory (HBM) device) having a storage component is disclosed. The stacked memory device can include a first logic die, one or more memory dies, a second logic die, and one or more storage dies. The first logic die is coupled with the one or more memory dies and the second logic die through TSVs. The second logic die is coupled with the one or more storage dies through additional TSVs. The first logic die can issue commands to the one or more memory dies that cause the one or more memory dies to perform operations (e.g., read/write operations). The first logic die can also issue commands to the second logic die that cause the second logic die to issue commands to the one or more storage dies to perform operations.
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Patent Agency Ranking
公开(公告)号：US20250022849A1
公开(公告)日：2025-01-16
申请号：US18749416
申请日：2024-06-20
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Raghukiran Sreeramaneni , Nevil N. Gajera
IPC: H01L25/065 , G11C11/4072 , G11C11/4096 , H10B80/00
Abstract: System-in-packages (SiPs) having combined high bandwidth memory (HBM) devices, and associated systems and methods, are disclosed herein. In some embodiments, the SiP includes a base substrate (e.g., a silicon interposer), a processing unit carried by the base substrate, and a HBM device carried by the base substrate. The combined HBM device can be electrically coupled to the processing unit through one or more traces. Further, the combined HBM device can include an interface die, one or more volatile memory dies carried by the interface die (e.g., a volatile, main memory component), and one or more non-volatile memory dies carried by the one or more memory dies. The combined HBM device can also include a shared bus that is electrically coupled to the interface die, the volatile memory dies, and the non-volatile memory dies to establish communication paths therebetween.
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公开(公告)号：US20240281390A1
公开(公告)日：2024-08-22
申请号：US18410808
申请日：2024-01-11
Applicant: Micron Technology, Inc.
Inventor： Dong Uk Lee , Sujeet Ayyapureddi , Lingming Yang , Tyler J. Gomm
IPC: G06F13/16
CPC classification number: G06F13/1678 , G06F13/161 , G06F13/1694
Abstract: A memory device includes a stack of eight memory dies having an 8N architecture and a stack of four memory dies having a 4N architecture. A first half and a second half of the stack of eight memory dies can each include 32 channels divided equally across the first half of dies and across the second half of dies. Banks of each of the 32 channels on the first half of dies can be associated with respective first pseudo channels. Banks of each of the 32 channels on the second half of dies can be associated with respective second pseudo channels. The stack of four memory dies can include the 32 channels divided equally amongst the dies, and the banks of each of the 32 channels on the stack of four memory dies can be divided equally across the respective first and second pseudo channels.
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公开(公告)号：US20230267996A1
公开(公告)日：2023-08-24
申请号：US18310736
申请日：2023-05-02
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Xuan Anh Tran , Karthik Sarpatwari , Francesco Douglas Verna-Ketel , Jessica Chen , Nevil N. Gajera , Amitava Majumdar
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/0028 , G11C13/0069 , G11C13/0026 , G11C2013/0092
Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.
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公开(公告)号：US20230236934A1
公开(公告)日：2023-07-27
申请号：US17894893
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Amitava Majumdar , Sandeep Krishna Thirumala , Nevil Gajera
CPC classification number: G06F11/1096 , G06F3/0619 , G06F3/0659 , G06F3/0689
Abstract: Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.
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公开(公告)号：US20230048450A1
公开(公告)日：2023-02-16
申请号：US17980382
申请日：2022-11-03
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Nevil N. Gajera , Lingming Yang , John F. Schreck
Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.
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