公开(公告)号：US11222695B2

公开(公告)日：2022-01-11

申请号：US16685349

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Rajasekhar Venigalla

IPC: G11C5/02 ,  G11C13/00 ,  H01L23/528 ,  H01L23/522 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

公开(公告)号：US20240282702A1

公开(公告)日：2024-08-22

申请号：US18652079

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H10B61/00 ,  H10B63/84

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US11996336B2

公开(公告)日：2024-05-28

申请号：US17714770

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Mallesh Rajashekharaiah

IPC: H01L21/00 ,  H01J37/28 ,  H01L21/66 ,  H01L21/768 ,  H01L23/528 ,  H10B63/00 ,  G11C13/00 ,  H01J37/04 ,  H10N70/00 ,  H10N70/20

CPC classification number: H01L22/12 ,  H01J37/28 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5283 ,  H10B63/84 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01J37/04 ,  H01J2237/2804 ,  H01J2237/2814 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8825

Abstract: Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

公开(公告)号：US11990370B2

公开(公告)日：2024-05-21

申请号：US18048633

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76883 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US20230298951A1

公开(公告)日：2023-09-21

申请号：US17696261

申请日：2022-03-16

Applicant: Micron Technology, Inc.

Inventor： Chase M. Hunter ,  Marlon W. Hug ,  Stephen W. Russell ,  Rajesh Kamana ,  Amitava Majumdar ,  Radhakrishna Kotti ,  Ahmed N. Noemaun ,  Tejaswi K. Indukuri

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L22/32 ,  H01L22/12

Abstract: Test structures for wafers are disclosed. A device may include a silicon wafer including a number of die and a scribe area between two die of the number of die. The scribe area may include one or more test structures. The test structures may include a p-doped region and an n-doped region adjacent to the p-doped region. The test structures may also include a first contact electrically coupled to the p-doped region and a second contact electrically coupled to the n-doped region. The second contact may be proximate to the first contact. Associated devices, systems, and methods are also disclosed.

公开(公告)号：US11302589B2

公开(公告)日：2022-04-12

申请号：US16700976

申请日：2019-12-02

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Mallesh Rajashekharaiah

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/768 ,  H01L27/24 ,  H01J37/28 ,  H01L23/528 ,  H01J37/04 ,  G11C13/00 ,  H01L45/00

Abstract: Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

公开(公告)号：US20220020446A1

公开(公告)日：2022-01-20

申请号：US17387290

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Patrick Daniel White ,  Pavan Reddy K. Aella ,  Rajesh Kamana

IPC: G11C29/38 ,  G11C29/44 ,  H01L21/66 ,  H04B17/354 ,  H04B1/525 ,  G11C5/06 ,  G06F3/06

Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

公开(公告)号：US11081203B2

公开(公告)日：2021-08-03

申请号：US16684533

申请日：2019-11-14

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Patrick Daniel White ,  Pavan Reddy K Aella ,  Rajesh Kamana

IPC: G11C29/38 ,  H01L21/66 ,  G11C29/44 ,  H04B17/354 ,  H04B1/525 ,  G11C5/06 ,  G06F3/06

Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

公开(公告)号：US20210166979A1

公开(公告)日：2021-06-03

申请号：US16700976

申请日：2019-12-02

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Mallesh Rajashekharaiah

IPC: H01L21/66 ,  H01L23/528 ,  H01L21/768 ,  H01L27/24 ,  H01J37/28

Abstract: Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.