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    APPARATUS AND METHODS FOR TESTING DEVICES
    21.
    发明申请
    APPARATUS AND METHODS FOR TESTING DEVICES 审中-公开

    公开(公告)号：US20170356946A1

    公开(公告)日：2017-12-14

    申请号：US15606109

    申请日：2017-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Paul E. Gregory ,  Randon K. Richards

    IPC: G01R31/00 ,  G01R1/067

    Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.

    MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT
    26.
    发明申请
    MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT 有权

    公开(公告)号：US20210367057A1

    公开(公告)日：2021-11-25

    申请号：US17391920

    申请日：2021-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Thomas H. Kinsley ,  Randon K. Richards

    IPC: H01L29/66 ,  H01L23/495 ,  H05K1/11 ,  H01L23/14 ,  H05K1/18

    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

    Memory device capable of adjusting clock signal based on operating speed and propagation delay of command/address signal
    28.
    发明授权
    Memory device capable of adjusting clock signal based on operating speed and propagation delay of command/address signal 有权

    公开(公告)号：US10943628B2

    公开(公告)日：2021-03-09

    申请号：US16518767

    申请日：2019-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Randon K. Richards ,  Dirgha Khatri

    IPC: G11C7/22 ,  G11C8/18 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4093

    Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

    METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    29.
    发明申请
    METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 有权

    公开(公告)号：US20210035617A1

    公开(公告)日：2021-02-04

    申请号：US16530739

    申请日：2019-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Eric J. Stave ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Chan H. Yoo ,  Randon K. Richards ,  Timothy M. Hollis

    IPC: G11C7/22 ,  G11C7/10 ,  G11C16/10

    Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

    METHODS FOR CLOCK SIGNAL ALIGNMENT IN A MEMORY DEVICE AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    30.
    发明申请
    METHODS FOR CLOCK SIGNAL ALIGNMENT IN A MEMORY DEVICE AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 有权

    公开(公告)号：US20210027816A1

    公开(公告)日：2021-01-28

    申请号：US16518767

    申请日：2019-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Randon K. Richards ,  Dirgha Khatri

    IPC: G11C7/22 ,  G06F13/16 ,  G11C8/18

    Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

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